Patents by Inventor Nunzia Malagnino

Nunzia Malagnino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178054
    Abstract: A body of semiconductor material has a surface and accommodates an active area, conductive regions, a first deep insulation structure extending in the active area from the surface of the body in a first trench, and a second deep insulation structure extending in the active area from the surface of the body in a second trench and surrounding the conductive regions. The first deep insulation structure has insulation walls surrounding a conductive filling portion. The second deep insulation structure has a solid insulating region filling the second trench. The first deep insulation region has a first width and a first depth and the second deep insulation structure has a second width and a second depth. The second width is smaller than the first width and the second depth is smaller than the first depth.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 30, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Emanuele LAGO, Nunzia MALAGNINO, Damiano RICCARDI
  • Patent number: 8062976
    Abstract: A method is for forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The method includes forming an opening through the dielectric layer and placing a solidifiable electrically conductive filler into the opening via a printing technique. The solidifiable electrically conductive filler is solidified to thereby form a solidified electrically conducting filler in the opening. A metallization layer is formed over the dielectric layer and the solidified electrically conducting filler to thereby form the vertical interconnection through the dielectric layer between the upper and lower electrically conductive layers of the integrated circuit.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: November 22, 2011
    Assignee: STMicroelectronics S.R.L.
    Inventors: Raffaele Vecchione, Luigi Giuseppe Occhipinti, Nunzia Malagnino, Rossana Scaldaferri, Maria Viviana Volpe
  • Publication number: 20110027986
    Abstract: A method is for forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The method includes forming an opening through the dielectric layer and placing a solidifiable electrically conductive filler into the opening via a printing technique. The solidifiable electrically conductive filler is solidified to thereby form a solidified electrically conducting filler in the opening. A metallization layer is formed over the dielectric layer and the solidified electrically conducting filler to thereby form the vertical interconnection through the dielectric layer between the upper and lower electrically conductive layers of the integrated circuit.
    Type: Application
    Filed: July 27, 2010
    Publication date: February 3, 2011
    Applicant: STMicroelectronics S.r.l.
    Inventors: Raffaele VECCHIONE, Luigi Giuseppe OCCHIPINTI, Nunzia MALAGNINO, Rossana SCALDAFERRI, Maria Viviana VOLPE
  • Publication number: 20090136820
    Abstract: A proton exchange membrane for electrolyte cells includes a polyelectrolyte polymer membrane comprising a sulfonated copolymer based on the following formula (I): wherein n is an integer between 1 and 1,000,000, and m is an integer between 1 and 1,000,000. A membrane-electrode assembly includes such a membrane.
    Type: Application
    Filed: May 30, 2008
    Publication date: May 28, 2009
    Applicant: STMicroelectronics S.r.l.
    Inventors: Teresa Napolitano, Nunzia Malagnino, Anna Borriello, Giuseppe Mensitieri