Patents by Inventor Oana Baltaretu

Oana Baltaretu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8438003
    Abstract: A method of improved simulator processing is provided. The method according to the current invention includes grouping frequently accessed data into one set id to improve memory hierarchy performance. The method further includes simulating predication in a non-predicated architecture to improve CPU performance. The simulated predication includes pseudo-predicated implementation of read-operation vector element access pseudo-predicated implementation of write-operation vector element access, and predicated implementation of multi-way branches with assignment statements having a same left-hand-side (lhs). The method further includes determining a selection path in a multi-sensitive “always” block to reduce taken branches. The multi-sensitive “always” block selection path determination includes generating instance-specific code to save port allocation storage, and generating inlined instance-specific code to combine sensitive actions.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: May 7, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Rakesh Agarwal, Oana Baltaretu
  • Publication number: 20090037161
    Abstract: A method of improved simulator processing is provided. The method according to the current invention includes grouping frequently accessed data into one set id to improve memory hierarchy performance. The method further includes simulating predication in a non-predicated architecture to improve CPU performance. The simulated predication includes pseudo-predicated implementation of read-operation vector element access pseudo-predicated implementation of write-operation vector element access, and predicated implementation of multi-way branches with assignment statements having a same left-hand-side (lhs). The method further includes determining a selection path in a multi-sensitive “always” block to reduce taken branches. The multi-sensitive “always” block selection path determination includes generating instance-specific code to save port allocation storage, and generating inlined instance-specific code to combine sensitive actions.
    Type: Application
    Filed: April 14, 2008
    Publication date: February 5, 2009
    Inventors: Rakesh Agarwal, Oana Baltaretu
  • Patent number: 6437780
    Abstract: A geometry tiler identifies tiles on a computer's screen that are covered by a graphics primitive by use of edges of the graphics primitive. Precise identification of tiles of various types (such as edge tiles covered by a segment) eliminates identification of one or more tiles that are merely located adjacent to the graphics primitive, but are not touched by the graphics primitive. For example, the geometry tiler can identify each of three types of tiles: vertex tiles, edge tiles and interior tiles.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: August 20, 2002
    Assignee: Nvidia US Investment Company
    Inventors: Oana Baltaretu, David L. Dignam, Sanjay O. Gupta