Abstract: A multi-link device (MLD) apparatus, including at least two transmission queues and first medium access control (MAC) circuitry and second MAC circuitry. The first MAC circuitry and the second MAC circuitry can transmit data of the at least two transmission queues over respective links responsive to receiving a trigger indicating that a transmission opportunity (TXOP) is available on the link corresponding to the respective first MAC circuitry and second MAC circuitry.

Abstract: A wireless communication device including one or more processors configured to determine a device state; determine a data rate of a signal; determine a latency tolerance value based on the data rate and the device state; and generate a message comprising the latency tolerance value. The wireless communication device may further be configured to determined if the latency tolerance value is a duration associated with a device reception or transmission.

Abstract: Some demonstrative embodiments include devices, systems and/or methods of scanning wireless communication channels. For example, a device may include a controller to receive one or more energy indications corresponding to one or more frequency ranges within a wireless communication frequency band, wherein a frequency range of the frequency ranges at least partially covers a plurality of wireless communication frequency channels, and wherein the controller is to scan for at least one wireless communication beacon over one or more channels of the plurality of wireless communication frequency channels, if an energy indication corresponding to the frequency range indicates wireless communication activity over the frequency range.

Abstract: A transmit and receive machine (TRM) is part of a medium access controller (MAC), in support of the 802.11 wireless standard. The TRM is a control machine that changes the MAC within which it resides from a purely software-based MAC into a software and hardware management system. Timing-critical tasks that were once performed by the embedded processor of the MAC are performed by the TRM. This change enables the MAC to operate at a high speed while the TRM maintains high accuracy of transmit and receive timing operations.

Abstract: A transmit and receive machine (TRM) is part of a medium access controller (MAC), in support of the 802.11 wireless standard. The TRM is a control machine that changes the MAC within which it resides from a purely software-based MAC into a software and hardware management system. Timing-critical tasks that were once performed by the embedded processor of the MAC are performed by the TRM. This change enables the MAC to operate at a high speed while the TRM maintains high accuracy of transmit and receive timing operations.

Abstract: A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural format to an internal format and data output in the internal format to the architectural format based on an operation code and a data type of a microinstruction.

Abstract: Embodiments of the present invention provide a method, apparatus and system of radar detection. The method, according to some demonstrative embodiments of the invention, may include comparing an energy level of signals received over a wireless communication channel to a threshold; during operation of a processor, if the energy level is above the threshold, determining independently of the processor one or more time values related to said signals; and if the energy level decreases to or below the threshold, interrupting the operation of the processor to determine, based on the time values, one or more parameters of a detection time period during which the energy level was above the threshold. Other embodiments are described and claimed.

Abstract: A method and apparatus for an apparatus and method for reduction of power consumption in OS that use flat segmentation memory model are described. In one embodiment, the method includes monitoring a segment register to detect a segment register update operation. Once the segment register update operation is detected, a code/data segment contained within the segment register is identified as one of a segmented code/data segment and a flat code/data segment. Once detected, the segment register is updated according to whether the segment is flat or segmented. Accordingly, when a segment register read is performed, one or more updated bits within the segment register are used to identify the code/data read from the segment register as either flat or segmented.

Abstract: Embodiments of the present invention provide a method, apparatus and system of radar detection. The method, according to some demonstrative embodiments of the invention, may include comparing an energy level of signals received over a wireless communication channel to a threshold; during operation of a processor, if the energy level is above the threshold, determining independently of the processor one or more time values related to said signals; and if the energy level decreases to or below the threshold, interrupting the operation of the processor to determine, based on the time values, one or more parameters of a detection time period during which the energy level was above the threshold. Other embodiments are described and claimed.

Abstract: A method and apparatus for an apparatus and method for reduction of power consumption in OS that use flat segmentation memory model are described. In one embodiment, the method includes monitoring a segment register to detect a segment register update operation. Once the segment register update operation is detected, a code/data segment contained within the segment register is identified as one of a segmented code/data segment and a flat code/data segment. Once detected, the segment register is updated according to whether the segment is flat or segmented. Accordingly, when a segment register read is performed, one or more updated bits within the segment register are used to identify the code/data read from the segment register as either flat or segmented.

Abstract: A method and apparatus for an apparatus and method for reduction of power consumption in OS that use flat segmentation memory model are described. In one embodiment, the method includes monitoring a segment register to detect a segment register update operation. Once the segment register update operation is detected, a code/data segment contained within the segment register is identified as one of a segmented code/data segment and a flat code/data segment. Once detected, the segment register is updated according to whether the segment is flat or segmented. Accordingly, when a segment register read is performed, one or more updated bits within the segment register are used to identify the code/data read from the segment register as either flat or segmented.

Abstract: A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural format to an internal format and data output in the internal format to the architectural format based on an operation code and a data type of a microinstruction.

Abstract: In some embodiments of the present invention, a processor includes a reservation station having one or more source ports and two or more layout stacks each having one or more execution units. Each execution unit is assigned to a source port. The processor may be able to drive one or more operands of a micro-instruction via one of the source ports to an execution unit in a layout stack without driving the operands to execution units in other layout stacks that are assigned to the same source port.

Abstract: A method and apparatus for an apparatus and method for reduction of power consumption in OS that use flat segmentation memory model are described. In one embodiment, the method includes monitoring a segment register to detect a segment register update operation. Once the segment register update operation is detected, a code/data segment contained within the segment register is identified as one of a segmented code/data segment and a flat code/data segment. Once detected, the segment register is updated according to whether the segment is flat or segmented. Accordingly, when a segment register read is performed, one or more updated bits within the segment register are used to identify the code/data read from the segment register as either flat or segmented.