Abstract: In a storage system including a first tier and a second tier a method includes: storing access statistics per object; obtaining a request to perform a write operation; calculating a recency factor to the first object based on the access statistics; and writing the first object to one of the first tier and the second tier, depending on the recency factor. Performing garbage collection process on the second tier may include: reading metadata of an object stored in the second tier; determining whether the object is valid based on the metadata; if the object is invalid, discarding the object; and if the second object is valid: calculating a recency factor for the object based on the access statistics of the object; and moving the object to the first tier or leaving the object in the second tier, depending on the recency factor of the second object.

Abstract: A system and method for performing a combined storage operation, the method including using a direct memory access (DMA) controller to obtain a modified DMA command, wherein the modified DMA command includes parameters of a data manipulation and one of a user read command or a user write command; retrieve data according to the user read command or the user write command; manipulate the data according to the parameters of a data manipulation, inline with the user read command or the user write command; and transmit the manipulated data according to the user read command or the user write command.

Abstract: A computer-based system and method for providing a distributed write buffer in a storage system, including: obtaining a write request at a primary storage server to store data associated with the write request in a non-volatile storage of the primary storage server; and storing the data associated with the write request in a persistent memory of the primary storage server or in a persistent memory of an auxiliary storage server based on presence of persistent memory space in the primary storage server. The write request may be acknowledged by the primary storage server after storing the data associated with the write request in the persistent memory of the primary storage server or in the persistent memory of the auxiliary storage server.

Abstract: Systems and methods of managing data storage, on non-volatile memory (NVM) media, by at least one processor may include: receiving a first storage request, to store a first data block on the NVM media; storing content of the first data block on a cache memory module; scheduling a future movement action of the content of the first data block from the cache memory module to the NVM media; and moving, transmitting or copying the content of the first data block from the cache memory module to at least one NVM device of the NVM media, according to the scheduled movement action.

Abstract: computer-based system and method for selecting a write unit size for a block storage device, includes performing a plurality of sequences of I/O operations to the block storage device, each sequence having a write unit size from a plurality of write unit sizes; collecting performance metrics of the sequences of I/O operations; and selecting the write unit size for the block storage device from the plurality of write unit sizes based on the performance metrics. In some cases, preconditioning is performed prior to performing the plurality of sequences of I/O operations by emptying the block storage device; and writing data to the block storage device to fill the block storage device above a predetermined level.

Abstract: A method and a system for accelerating computer data garbage collection (GC) on a non-volatile memory (NVM) computer storage device may include: monitoring, by a processor, a data validity parameter of at least one physical write unit (PWU), where the PWU may include a plurality of physical data pages of the NVM device; sending at least one GC command from the processor to an accelerator associated with the NVM device, based on the monitored data validity parameter; copying, by the accelerator, a plurality of data-objects stored on at least one first PWU, to a read address space comprised within the accelerator; copying valid data-objects from the read address space to a write address space comprised within the accelerator until the amount of data in the write address space exceeds a predefined threshold; and storing, by the accelerator, the data content in at least one second PWU in the NVM media.

Abstract: A system and a method of balancing a load of access of at least one computing device to an arbitrary integer number of connected memory devices associated with a memory cluster address space, the method including: determining, by a controller, a number N corresponding to an arbitrary integer number of memory devices connected to a plurality of memory interfaces, wherein N is between 1 and the number of memory interfaces; receiving, by the controller, at least one data object, corresponding to an original processor address (OPA) from the at least one computing device; computing, by the controller, at least one interleaving function according to N; and mapping, by an interleaving circuit, the OPA to a memory cluster address (MCA), according to the at least one interleaving function, so that the data object is equally interleaved among the N connected devices.

Abstract: A method for data communication includes submitting from a host processor to a network interface controller (NIC) during a first time period first work items instructing the NIC to transmit over a network packets containing respective data. The first work items include pointer-based work items, which contain a pointer to the respective data in a memory of the host processor, and inline work items, which contain the respective data. The performance of the NIC is measured in transmitting the packets during the first time period. During a second time period, subsequent to the first time period, the host processor submits second work items to the NIC while deciding automatically, under control of software running on the host processor and based on the measured performance during the first time period, how many of the second work items are to be pointer-based and how many are to be inline work items.

Abstract: A Network Interface Controller (NIC) includes a network interface, a peer interface and steering logic. The network interface is configured to receive incoming packets from a communication network. The peer interface is configured to communicate with a peer NIC not via the communication network. The steering logic is configured to classify the packets received over the network interface into first incoming packets that are destined to a local Central Processing Unit (CPU) served by the NIC, and second incoming packets that are destined to a remote CPU served by the peer NIC, to forward the first incoming packets to the local CPU, and to forward the second incoming packets to the peer NIC over the peer interface not via the communication network.

Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more work requests that are derived from an operation to be executed by the node. The NI maintains a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the work requests via the host interface, and to execute the work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Abstract: A method for data communication includes submitting from a host processor to a network interface controller (NIC) during a first time period first work items instructing the NIC to transmit over a network packets containing respective data. The first work items include pointer-based work items, which contain a pointer to the respective data in a memory of the host processor, and inline work items, which contain the respective data. The performance of the NIC is measured in transmitting the packets during the first time period. During a second time period, subsequent to the first time period, the host processor submits second work items to the NIC while deciding automatically, under control of software running on the host processor and based on the measured performance during the first time period, how many of the second work items are to be pointer-based and how many are to be inline work items.

Abstract: A method for communication includes posting, by a software process, a set of buffers in a memory of a host processor and creating in the memory a list of labels associated respectively with the buffers. The software process pushes a first part of the list to a network interface controller (NIC), while retaining a second part of the list in the memory under control of the software process. Upon receiving a message containing a label, sent over a network, the NIC compares the label to the labels in the first part of the list and, upon finding a match to the label, writes data conveyed by the message to a buffer in the memory. Upon a failure to find the match in the first part of the list, the NIC passes the message from the NIC to the software process for handling using the second part of the list.

Abstract: A method for network access of remote memory directly from a local instruction stream using conventional loads and stores. In cases where network IO access (a network phase) cannot overlap a compute phase, a direct network access from the instruction stream greatly decreases latency in CPU processing. The network is treated as yet another memory that can be directly read from, or written to, by the CPU. Network access can be done directly from the instruction stream using regular loads and stores. Example scenarios where synchronous network access can be beneficial are SHMEM (symmetric hierarchical memory access) usages (where the program directly reads/writes remote memory), and scenarios where part of system memory (for example DDR) can reside over a network and made accessible by demand to different CPUs.

Abstract: A network interface includes a host interface for communicating with a node, and circuitry which is configured to communicate with one or more other nodes over a communication network so as to carry out, jointly with one or more other nodes, a redundant storage operation that includes a redundancy calculation, including performing the redundancy calculation on behalf of the node.

Abstract: A method for communication includes posting, by a software process, a set of buffers in a memory of a host processor and creating in the memory a list of labels associated respectively with the buffers. The software process pushes a first part of the list to a network interface controller (NIC), while retaining a second part of the list in the memory under control of the software process. Upon receiving a message containing a label, sent over a network, the NIC compares the label to the labels in the first part of the list and, upon finding a match to the label, writes data conveyed by the message to a buffer in the memory. Upon a failure to find the match in the first part of the list, the NIC passes the message from the NIC to the software process for handling using the second part of the list.

Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more work requests that are derived from an operation to be executed by the node. The NI maintains a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the work requests via the host interface, and to execute the work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Abstract: A Network Interface Controller (NIC) includes a network interface, a peer interface and steering logic. The network interface is configured to receive incoming packets from a communication network. The peer interface is configured to communicate with a peer NIC not via the communication network. The steering logic is configured to classify the packets received over the network interface into first incoming packets that are destined to a local Central Processing Unit (CPU) served by the NIC, and second incoming packets that are destined to a remote CPU served by the peer NIC, to forward the first incoming packets to the local CPU, and to forward the second incoming packets to the peer NIC over the peer interface not via the communication network.

Abstract: A method for network access of remote memory directly from a local instruction stream using conventional loads and stores. In cases where network IO access (a network phase) cannot overlap a compute phase, a direct network access from the instruction stream greatly decreases latency in CPU processing. The network is treated as yet another memory that can be directly read from, or written to, by the CPU. Network access can be done directly from the instruction stream using regular loads and stores. Example scenarios where synchronous network access can be beneficial are SHMEM (symmetric hierarchical memory access) usages (where the program directly reads/writes remote memory), and scenarios where part of system memory (for example DDR) can reside over a network and made accessible by demand to different CPUs.

Abstract: A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.

Abstract: A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to generate completion reports and to write a plurality of the completion reports to the system memory via the bus together in a single bus transaction.