Abstract: Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a scrambler configured to provide a driving address and associated data to an envelope based on a memory configuration for using a memory array. The driving address and the associated data are used to test the memory array according to a test pattern. The envelope is configured to translate the driving address into a corresponding physical address of the memory array based on the memory configuration.

Abstract: Aspects of the disclosure provide an integrated circuit that is configured for parallel memory testing. The integrated circuit includes a first memory block and a first scrambler coupled to the first memory block during a memory testing. The first memory block includes a first memory array, and a first envelope configured to translate a driving address of the first memory block into a corresponding physical address of the first memory array based on a first memory configuration for using the first memory array. The first scrambler is configured to provide a first plurality of driving addresses and associated first data to the first envelope based on the first memory configuration. The first plurality of driving addresses and the first data are used to test the first memory array according to a first test pattern. Further, the integrated circuit includes a second memory block and a second scrambler coupled to the second memory block during the memory testing.