Abstract: A method of processing instructions having register dependencies in a pipelined superscalar processor comprises the steps of fetching operands specified by a first instruction during a first pipestage, then computing address of a source operand for a second instruction so that the subsequent instruction can be processed without incurring data errors. A status bit of a destination register of the first instruction is checked during the decoding stages of the second instruction to determine whether the register is busy or free for use in performing the operation specified. In the case where the register is busy, processing of the subsequent instruction is temporarily frozen. In another situation, a result obtained by a first instruction is provided as a source operand for the second instruction so that the second instruction can be executed without delay.

Abstract: A method and apparatus for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file. According to one aspect of the invention, a processor is provided that includes at least two physical register files--one for executing scalar data type operations and the other for executing packed data type operations. In addition, the processor includes a transition unit that is configured to cause the two physical register files to logically appear to software executing on the processor as a single logical register file.

Abstract: The invention provides a method and apparatus for providing operand reads in a processor pipeline. According to one aspect of the invention, a method is described for executing an instruction in a computer pipeline that requires different operands be read from the same register file in different stages of the computer pipeline. According to another aspect of the invention, a method is described for executing an instruction in a processor pipeline. According to this method, at least a first operand is read from a register file in a first stage of the processor pipeline. If execution of the instruction causes the processor to place the first operand in a storage area other than the register file, then the first operand in written to that storage area in a subsequent stage of the processor pipeline. Otherwise, one or more ALU operations are performed on the first operand and at least a second operand in a different subsequent stage of the processor pipeline.

Abstract: A superscalar processor has two pipelines that include decode, operand read, execute and writeback stages. An instruction datapath circuit of the processor comprises a plurality of result buses coupled to a corresponding plurality of write ports of a register file. Read ports of the register file are coupled to multiplexer logic which selects operands for various operations specified by instructions. Execution results of the operations are provided on the result buses. Each register of the register file has a status bit that is set responsive to a multiplication operation which specifies data stored in the register. The status bit is reset responsive to generation of a product from the multiplication operation. Processing of a latter instruction in the pipelines is halted when the latter instruction specifies the register and the status bit is set. Also included is a bypass mechanism that allows a result produced during the execute stage to be bypassed to the read stage of a subsequent instruction.