Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract: A display apparatus includes a plurality of pixels. A pixel includes a first capacitor connected between a first voltage line receiving a first driving signal and a first node, a first transistor comprising a control electrode connected to the first node, a first electrode connected to a second voltage line receiving a first power source signal and a second electrode connected to a second node, an organic light emitting diode comprising an anode electrode connected to the second node and a cathode electrode receiving a second power source signal, a second capacitor connected between an m-th data line and the second node (wherein, ‘m’ is a natural number) and a second transistor comprising a control electrode connected to an n-th scan line (wherein, ‘n’ is a natural number), a first electrode connected to the first node and a second electrode connected to the second node.

Abstract: A data driver capable of displaying images with a substantially uniform brightness, an organic light emitting display device using the same, and a method of driving the organic light emitting display device. The data driver includes a plurality of current sink units for controlling predetermined currents to flow through data lines, a plurality of voltage generators for resetting values of gray scale voltages using compensation voltages generated when the predetermined currents flow, a plurality of digital-to-analog converters for selecting one gray scale voltage among the gray scale voltages as a data signal in response to bit values of the data supplied from the outside, and a plurality of switching units for supplying the data signal to the data lines. The predetermined currents may be set equal to pixel currents that correspond to a maximum brightness.

Abstract: An analog to digital converting device includes an analog to digital converting unit suitable for converting an image signal into a digital signal; and a digital arithmetic unit suitable for calculating a difference between a reset voltage and a signal voltage, which correspond to the digital signal.

Abstract: An analog-digital converting device includes a successive approximation register (SAR) analog-digital converting circuit suitable for resolving upper N-bits for an input signal, a single-slope (SS) analog-digital converting circuit suitable for resolving lower M-bits for the input signal after the SAR analog-digital converting circuit resolves the upper N-bits, and a combining circuit suitable for combining the upper N-bits and the lower M-bits.

Abstract: A pixel includes an organic light emitting diode and a pixel control circuit. The pixel control circuit includes a first transistor, a second transistor, and a third transistor. The first transistor controls an amount of current to the organic light emitting diode from a first power source based on a voltage applied to a first node. The second transistor is coupled between the first node and a data line and turns on when a scan signal is supplied to a scan line. The third transistor is coupled between the first power source and a second node that is a common terminal of first and second capacitors, which are coupled in series between the first node and the first power source. In operation, the third transistor turns on when a first control signal is supplied to a first control line.

Abstract: An analog to digital converting device includes an analog to digital converting unit suitable for converting an image signal into a digital signal; and a digital arithmetic unit suitable for calculating a difference between a reset voltage and a signal voltage, which correspond to the digital signal.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract: Arithmetic memories, image sensors including the arithmetic memories and methods of operating the arithmetic memories are provided. The arithmetic memories may include an input block to which a digital pixel reset signal and a digital pixel image signal are input and a plurality of unit cells configured to generate a digital difference signal. The input block may include first and second multiplexers to which the digital pixel reset signal and the digital pixel image signal are input and an inverter connected to the first multiplexer. The plurality of unit cells may include a first unit cell connected to the input block and a second unit cell through an N-th unit cell successively connected to the first unit cell. N may be two or greater. The first unit cell may include third and fourth multiplexers, a first flip/flop, and a first AND gate.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract: A data transmitter may include a transmitter circuit and a calibration controller. The transmitter circuit is configured to be coupled to a receiver through a channel, and configured to provide an output signal to the channel based on an input signal and adjust an output impedance value according to a bias signal. The calibration controller is configured to adjust the bias signal by comparing the output signal of the transmitter circuit to a reference signal during a calibration operation.

Abstract: A method of driving a display device including a sensing line, a light-emitting element, a capacitor, and a driving transistor, the driving transistor comprising a control terminal that is connected to the capacitor, an input terminal, and an output terminal, the method including: connecting the control terminal and the output terminal; connecting the control terminal and the output terminal to a ground voltage and then disconnecting the control terminal and the output terminal from the ground voltage; sensing a first voltage of the control terminal through the sensing line; and calculating a threshold voltage of the driving transistor based on the first voltage.

Abstract: A gate driver, including multiple stages of gate driving circuits, wherein each stage of the gate driving circuits includes an input part configured to generate a Q node signal in response to a carry signal of one of previous stages and a clock signal, the Q node signal being applied to Q node, an output part configured to output a gate output signal to a gate output terminal in response to the Q node signal, and a charge sharing part connected to the gate output terminal of a present stage and a gate output terminal of one of next stages, the charge sharing part configured to operate charge-sharing between the gate output signal of the present stage and a gate output signal of one of the next stages in response to a select signal.

Abstract: An analog-to-digital converter includes an upper bit conversion unit suitable for receiving an input signal, and sampling upper bits from the input signal, a lower bit conversion unit suitable for receiving a residual voltage remaining after the sampling of the upper bit conversion unit, and sampling lower bits from the residual voltage, and an error correction unit suitable for correcting an error of the sampled upper bits and the sampled lower bits.

Abstract: An analog-to-digital converter includes a digital-to-analog converter comprising a capacitor divider network comprising a plurality of dividing capacitors and a dummy capacitor. The digital-to-analog converter is configured to selectively apply an input voltage and a reference voltage to the dividing capacitors and to selectively apply the input voltage and a shift voltage to the dummy capacitor. The analog-to-digital converter further includes a comparison circuit configured to compare an output of the capacitor divider network and a common mode voltage and a shift voltage generator circuit configured to generate the shift voltage. The shift voltage generator circuit may be configured to vary the shift voltage for different samples of the input voltage. For example, the shift voltage generator circuit may be configured to change the shift voltage for succeeding samples by an amount corresponding to 1/(2^M) times the reference voltage to support 2^M oversampling of the input voltage.

Abstract: A display device includes a plurality of display pixels, a plurality of data lines that are connected to the display pixels, and a plurality of sensing lines that are connected to the display pixels. Each display pixel includes a driving transistor comprising a first terminal, a second terminal, and a third terminal, a capacitor connected to the first terminal of the driving transistor, a first switching transistor connected to the data line and the first terminal of the driving transistor, a light-emitting element connected to the third terminal of the driving transistor configured to emit light, a second switching transistor connected between the sensing line and the light-emitting element, and a third switching transistor connected between the third terminal of the driving transistor and the light-emitting element.

Abstract: An analog-to-digital converter includes an upper bit conversion unit suitable for receiving an input signal, and sampling upper bits from the input signal, a lower bit conversion unit suitable for receiving a residual voltage remaining after the sampling of the upper bit conversion unit, and sampling lower bits from the residual voltage, and an error correction unit suitable for correcting an error of the sampled upper bits and the sampled lower bits.

Abstract: A pixel having a simplified structure can compensate for the threshold voltage of a driving transistor thereof. The pixel includes an organic light emitting diode (OLED) having a cathode electrode coupled to a second power source, a storage capacitor coupled between a data line and a first node, a second transistor having a first electrode coupled to a first power source, a second electrode coupled to an anode electrode of the OLED, and a gate electrode coupled to the first node, a first transistor coupled between the first node and the second electrode of the second transistor, a gate electrode of the first transistor being coupled to a current scan line, and a third transistor coupled between the second electrode of the second transistor and the anode electrode of the OLED, a gate electrode of the third transistor being coupled to a control line.

Abstract: A data transmitter may include a transmitter circuit and a calibration controller. The transmitter circuit is configured to be coupled to a receiver through a channel, and configured to provide an output signal to the channel based on an input signal and adjust an output impedance value according to a bias signal. The calibration controller is configured to adjust the bias signal by comparing the output signal of the transmitter circuit to a reference signal during a calibration operation.

Abstract: A pixel having a simplified structure can compensate for the threshold voltage of a driving transistor thereof. The pixel includes an organic light emitting diode (OLED) having a cathode electrode coupled to a second power source, a storage capacitor coupled between a data line and a first node, a second transistor having a first electrode coupled to a first power source, a second electrode coupled to an anode electrode of the OLED, and a gate electrode coupled to the first node, a first transistor coupled between the first node and the second electrode of the second transistor, a gate electrode of the first transistor being coupled to a current scan line, and a third transistor coupled between the second electrode of the second transistor and the anode electrode of the OLED, a gate electrode of the third transistor being coupled to a control line.