Abstract: Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.

Abstract: An address signal transition detecting apparatus includes an address transition detecting circuit for detecting transitions in address signals, accordingly generating address transition detection signals and summing the address transition detection signals to generate an address transition detection sum signal ATDSUM, respectively outputting a first pulse signal YE for activating a column address decoder, a second pulse signal P for activating a precharger and a third pulse signal SE for activating a sense amplifier in accordance with an address transition detecting sum signal ATDSUM, and once again outputting another first pulse signal YE for activating the column address decoder in response to a fourth pulse signal YE2 generated in accordance with the address transition detection sum signal ATDSUM and the first pulse signal YE.

Abstract: A circuit for generating equalization pulses for a memory device is disclosed, which prevents formation of a short circuit between a Vdd potential and a Vss potential when two address transition signals are successively generated, and which generates the equalization pulses by using address transition pulses and by reducing the access time of the memory device. The equalization pulse generating circuit includes a NAND circuit section for outputting a NAND logic of address transition signals under address transitions to an equalization pulse generating node, a delay circuit section for delaying an output of the equalization pulse generating node for a certain period of time, so as to generate at least one delayed output signal, and a maintaining circuit section for logically processing the delayed output signal of the delay circuit section and the NAND logic output of the NAND circuit section, so as to maintain the state of the equalization pulse generating node in the same state for a certain period of time.

Abstract: A sense amplifier for a memory which is capable of preventing a ground bouncing and waste of electric power generated in a column sense amplifier where a column selection signal is enabled and a word line is disabled, by connecting a switching element to each ground terminal of the column sense amplifiers included in each cell array block, which includes a plurality of cell array blocks; and a plurality of switching circuits for stabilizing ground voltages of the cell array blocks by being switched in accordance with each switching signal being enabled when a word line is enabled, and respectively controlling ground current of the cell array blocks.

Abstract: In an alignment structure of a main amplifier in a memory device, main amplifiers are aligned between memory cell arrays, so that the data line is shortened from the selected column switch to the main amplifier, to thereby reduce power consumption.