Abstract: A liquid crystal display includes a plurality of pixels, a plurality of data lines connected to the plurality of pixels, and a data driver connected to the plurality of data lines, where the data driver supplies data voltage to the plurality of data lines, where the data driver includes a data latch which outputs input image data in response to image data corresponding to the plurality of pixels, wherein the data latch rearranges a sequence of the image data, and a digital-to-analog converting unit which includes a positive digital-to-analog converter which generates a positive data voltage in response to the input image data, and a negative digital-to-analog converter which generates a negative data voltage in response to the input image data.

Abstract: A gate driver includes a gate integrated circuit (“IC”) chip which receives at least two scanning start signals and at least four clock control signals, and outputs a plurality of gate-on voltages, where at least two clock control signals of the at least four clock control signals are generated based on one scanning start signal of the at least two scanning start signals, timings of the at least two scanning start signals are independent of each other, and timings of the at least two clock control signals based on the one scanning start signal are independent of each other.

Abstract: A gate driver includes a gate integrated circuit (“IC”) chip which receives at least two scanning start signals and at least four clock control signals, and outputs a plurality of gate-on voltages, where at least two clock control signals of the at least four clock control signals are generated based on one scanning start signal of the at least two scanning start signals, timings of the at least two scanning start signals are independent of each other, and timings of the at least two clock control signals based on the one scanning start signal are independent of each other.

Abstract: A driving device of a display apparatus includes: a gate driver, a gate on voltage modulator, and a signal controller. The gate driver includes a plurality of gate driving circuits, each of the gate driving circuits being configured to: generate a gate signal according to a gate control signal, and apply the gate signal to at least one gate line. The gate on voltage modulator is configured to: modulate a gate on voltage according to a modulation control signal, and generate a first modulated gate on voltage. The signal controller is configured to generate the modulation control signal and the gate control signal. At least one of the plurality of gate driving circuits includes an amplifier configured to: receive the first modulated gate on voltage, and output a second modulated gate on voltage including substantially the same waveform as the first modulated gate on voltage.

Abstract: A display device includes an array substrate, a driving film and an adhesive member. The array substrate includes a first base substrate, a plurality of first signal pads formed on the first base substrate and a first dummy pad formed adjacent to the first signal pads. The driving film includes a base film, a plurality of output terminals formed on the base film and a first alignment mark formed adjacent to the output terminals. The adhesive member adheres the first signal pads to the output terminals, and adheres the first dummy pad to the first alignment mark.

Abstract: The data driving apparatus includes a gamma data storage unit storing p-bit gamma data, a conversion data storage unit storing q-bit gamma data corresponding to the p-bit gamma data, a gamma data conversion unit converting the p-bit gamma data into the q-bit gamma data based on the conversion data storage unit, and a gamma voltage generator generating gamma voltage from the q-bit gamma data, in which the conversion data storage unit is refreshed in a vertical blank period.

Abstract: A display device includes gate lines; data lines; charge control lines each including a charge control voltage input pad; first and second thin film transistors (TFTs) each including control and input electrodes connected to the gate and data lines, respectively; a first liquid crystal capacitor connected to an output electrode of the first TFT; a second liquid crystal capacitor connected to an output electrode of the second TFT; a charge control TFT including a control electrode and an input electrode connected to one of the charge control lines and the second pixel electrode, respectively; and a charge-down capacitor connected to an output electrode of the charge control TFT. A duration time of a turn-on voltage pulse applied to the charge control TFT is different from a duration time of a turn-on voltage pulse applied to the first TFT transistor or the second TFT.

Abstract: Provided is a liquid crystal display including: a liquid crystal panel, a plurality of display signal lines disposed in the liquid crystal panel, a plurality of diodes including a first diode and a second diode. The first diode is connected to each of the display signal lines in a reverse direction and the second diode is connected to each of the display signal lines in a forward direction. The liquid crystal display further includes a plurality of first dummy pads and a plurality of second dummy pads disposed on IC chips which are mounted on a film which is connected to the display panel. A first dummy voltage line is connected to the first dummy pads, a second dummy voltage line is connected to the second dummy pads, and the first dummy pads and the second dummy pads are each adapted to receive a driving voltage.

Abstract: A gate driver includes a gate integrated circuit (“IC”) chip which receives at least two scanning start signals and at least four clock control signals, and outputs a plurality of gate-on voltages, where at least two clock control signals of the at least four clock control signals are generated based on one scanning start signal of the at least two scanning start signals, timings of the at least two scanning start signals are independent of each other, and timings of the at least two clock control signals based on the one scanning start signal are independent of each other.

Abstract: A power circuit for a liquid crystal display includes a voltage divider which generates a voltage-divided voltage between a first power source and a second power source, an operational amplifier which receives the voltage-divided voltage to output a driving voltage, a first switch connected between the first power source and a common node, and a second switch connected between the second power source and the common node. The first switch provides a first current path between the first power source and the common node in response to the driving voltage, and the second switch provides a second current path between the second power source and the common node in response to the driving voltage.

Abstract: A display device includes an array substrate, a driving film and an adhesive member. The array substrate includes a first base substrate, a plurality of first signal pads formed on the first base substrate and a first dummy pad formed adjacent to the first signal pads. The driving film includes a base film, a plurality of output terminals formed on the base film and a first alignment mark formed adjacent to the output terminals. The adhesive member adheres the first signal pads to the output terminals, and adheres the first dummy pad to the first alignment mark.

Abstract: A liquid crystal display includes a plurality of pixels, a plurality of data lines connected to the plurality of pixels, and a data driver connected to the plurality of data lines, where the data driver supplies data voltage to the plurality of data lines, where the data driver includes a data latch which outputs input image data in response to image data corresponding to the plurality of pixels, wherein the data latch rearranges a sequence of the image data, and a digital-to-analog converting unit which includes a positive digital-to-analog converter which generates a positive data voltage in response to the input image data, and a negative digital-to-analog converter which generates a negative data voltage in response to the input image data.

Abstract: A display device includes a signal controller processing an input image signal and an input control signal and outputting an image signal and a control signal. A gray voltage generator generates reference gray voltages. The control signal includes a selection signal. A data driver generates gray voltages based on the reference gray voltage, selects a gray voltage corresponding to the image signal among the generated gray voltages, and applies the selected gray voltage to a pixel as a first data voltage. The data driver applies a black data voltage corresponding to a black image to the pixel according to the selection signal.

Abstract: In a display apparatus, a display panel displays an image, and a frame rate converter separates an image signal to a first image frame for a left-eye and a second image frame for a right-eye and generates first and second intermediate image frames respectively following the first and second image frames. A timing controller converts the first and second image frames to first and second compensation frames, respectively, and sequentially provides the first compensation frame, the first intermediate image frame, the second compensation frame, and the second intermediate image frame to a data driver. The data driver converts the first and second compensation frames to a left-eye data voltage and a right-eye data voltage, respectively, and converts the first and second intermediate image frames to a predetermined black data voltage.

Abstract: A display device having a reduced repair line length and a reduced repair unit to reduce the wire resistance of the repair line and the repair unit. The display device includes: a single flexible circuit film; a circuit board connected to the flexible circuit film; and a thin film transistor array panel connected to the flexible circuit film and having a display area and a peripheral area enclosing the display area. The display device also includes a single driving circuit chip disposed on the flexible circuit film; a repair line and a repair bar disposed in the peripheral area of the thin film transistor array panel; a repair amplifier disposed on the driving circuit chip and connected to the repair line and the repair bar. A repair input line connects the repair bar and the repair amplifier and a repair output line connects the repair amplifier and the repair line.

Abstract: A display device includes gate lines; data lines; charge control lines each including a charge control voltage input pad; first and second thin film transistors (TFTs) each including control and input electrodes connected to the gate and data lines, respectively; a first liquid crystal capacitor connected to an output electrode of the first TFT; a second liquid crystal capacitor connected to an output electrode of the second TFT; a charge control TFT including a control electrode and an input electrode connected to one of the charge control lines and the second pixel electrode, respectively; and a charge-down capacitor connected to an output electrode of the charge control TFT. A duration time of a turn-on voltage pulse applied to the charge control TFT is different from a duration time of a turn-on voltage pulse applied to the first TFT transistor or the second TFT.

Abstract: A display device includes a first unit pixel disposed in a first pixel column and a first pixel row, and a second unit pixel disposed in the first pixel column and a second pixel row adjacent to the first pixel row, and first and second gate lines extending in a row direction and having gate voltage input pads at a terminal portion thereof. First and second data lines extend in a column direction and are connected to the first unit pixel and the second unit pixel, respectively. A first charge control line extends in the row direction and has a charge control gate voltage input pad disposed at a terminal portion thereof. The first gate line is connected to the first unit pixel and the second gate line is connected to the second unit pixel. The first gate line and the second gate line simultaneously receive a same gate pulse.

Abstract: A power circuit for a liquid crystal display includes a voltage divider which generates a voltage-divided voltage between a first power source and a second power source, an operational amplifier which receives the voltage-divided voltage to output a driving voltage, a first switch connected between the first power source and a common node, and a second switch connected between the second power source and the common node. The first switch provides a first current path between the first power source and the common node in response to the driving voltage, and the second switch provides a second current path between the second power source and the common node in response to the driving voltage.