Abstract: A voltage divider circuit arrangement includes a resistive divider circuit portion constructed from first and second resistors (R1, R2) The first and second resistors are connected in series and are arranged to provide a refresh voltage (Vrefresh) at a refresh node between them. A capacitive divider circuit portion is constructed from first and second capacitors (C1, C2). The first and second capacitors are connected in series and are arranged to provide an output voltage (Vout) at an output node. A switching circuit portion is arranged intermittently to switch the voltage divider circuit arrangement between a first mode wherein the resistive divider is enabled and the output node is connected to the refresh node, and a second mode wherein the resistive divider is disabled and the output node is not connected to the refresh node.

Abstract: A duty cycle conversion circuit portion comprises N inverters, wherein N is an integer greater than two. The duty cycle conversion circuit is arranged to receive N input signals each having a duty cycle between 1/N and 2/N. Each of the N input signals is applied to a respective input terminal of one of the N inverters such that each inverter receives a different input signal. Each of the N input signals is applied to a respective power terminal of one of the N inverters such that each inverter is powered by a different input signal. Each inverter receives different input signal at its respective input terminal to the input signal applied to its respective power terminal.

Abstract: A voltage divider circuit comprises: a resistive divider circuit portion comprising at least first and second resistors (R1, R2), wherein said first and second resistors are connected in series and are arranged to provide a refresh voltage (Vrefresh) at a refresh node therebetween; a capacitive divider circuit portion comprising at least first and second capacitors (C1, C2), wherein said first and second capacitors are connected in series and are arranged to provide an output voltage (Vout) at an output node therebetween; and a switching circuit portion arranged intermittently to switch the voltage divider circuit arrangement between a first mode wherein the resistive divider circuit portion is enabled and the output node is connected to the refresh node, and a second mode wherein the resistive divider circuit portion is disabled and the output node is not connected to the refresh node.

Abstract: A duty cycle conversion circuit portion comprises N inverters, wherein N is an integer greater than two. The duty cycle conversion circuit is arranged to receive N input signals each having a duty cycle between 1/N and 2/N. Each of the N input signals is applied to a respective input terminal of one of the N inverters such that each inverter receives a different input signal. Each of the N input signals is applied to a respective power terminal of one of the N inverters such that each inverter is powered by a different input signal. Each inverter receives different input signal at its respective input terminal to the input signal applied to its respective power terminal.

Abstract: A method of demodulating an amplitude modulated radio signal is disclosed. The method comprises directing the modulated signal 302 to both a phase detector 308 and an edge detector 314, and using the respective output signals 310, 318, 320 of the phase detector 308 and edge detector 314 to determine an end of a modulation symbol 340 in the signal 302.

Abstract: A method of demodulating an amplitude modulated radio signal is disclosed. The method comprises directing the modulated signal 302 to both a phase detector 308 and an edge detector 314, and using the respective output signals 310, 318, 320 of the phase detector 308 and edge detector 314 to determine an end of a modulation symbol 340 in the signal 302.

Abstract: A radio transmitter (4) comprises an encoder (5) that receives one or more variable message bits, and encodes each message bit that has a first value as a predetermined first binary chip sequence and encodes each message bit that has the opposite value as a predetermined second binary chip sequence. The radio transmitter (4) transmits data packets, each comprising (i) a predetermined synchronization portion, comprising one or more instances of the first binary chip sequence, and (ii) a variable data portion, comprising one or more encoded message bits output by the encoder. A radio receiver (9) receives such data packets. It uses the synchronization portion of a received data packet to perform a frequency and/or timing synchronization operation, and then decodes message bits from the data portion of the data packet.

Abstract: A phase locked loop frequency synthesizer is arranged to provide a target frequency output signal for a radio transmitter or receiver. The synthesizer comprises: a voltage controlled oscillator (2) operating at a first frequency; a first, fixed frequency divider to provide a second frequency, a pre-scaler to provide a variable frequency division of said second frequency to produce a third frequency, said pre-scaler comprising: a second frequency divider (14) connected to said first output (12) and providing a second output at a second frequency; and a phase detector (4) controlling said voltage controlled oscillator (2) on the basis of a comparison between a reference signal and a signal dependent on said third frequency; wherein the synthesizer is configured so that said first output (10, 12) provides said target frequency output signal.

Abstract: A relaxation oscillator 2 comprises: a comparator 4 comprising: a differential pair of transistors 140, 142, 144. 40, 42, 44; a static current source 32; and a dynamic current source 32; and at least one energy storage component 8, 14; wherein the comparator 4 is arranged to provide an output signal which triggers the charging or discharging of the energy storage component 8, the dynamic current source 32 being enabled prior to the charging or discharging being triggered and disabled after a predetermined time.

Abstract: A differential comparator has a first input and a second input comprises: first and second transistors arranged as a differential pair connected to the first and second inputs respectively; and a constant current arrangement disposed between said differential pair and a first supply rail; wherein a first path between the first transistor and the constant current arrangement has a different resistance to a second path between the second transistor and the constant current arrangement. Also disclosed is a radio receiver employing such a differential comparator.

Abstract: A radio transmitter (4) comprises an encoder (5) that receives one or more variable message bits, and encodes each message bit that has a first value as a predetermined first binary chip sequence and encodes each message bit that has the opposite value as a predetermined second binary chip sequence. The radio transmitter (4) transmits data packets, each comprising (i) a predetermined synchronisation portion, comprising one or more instances of the first binary chip sequence, and (ii) a variable data portion, comprising one or more encoded message bits output by the encoder. A radio receiver (9) receives such data packets. It uses the synchronisation portion of a received data packet to perform a frequency and/or timing synchronisation operation, and then decodes message bits from the data portion of the data packet.

Abstract: A phase locked loop frequency synthesizer is arranged to provide a target frequency output signal for a radio transmitter or receiver. The synthesizer comprises: a voltage controlled oscillator (2) operating at a first frequency; a first, fixed frequency divider to provide a second frequency, a pre-scaler to provide a variable frequency division of said second frequency to produce a third frequency, said pre-scaler comprising: a second frequency divider (14) connected to said first output (12) and providing a second output at a second frequency; and a phase detector (4) controlling said voltage controlled oscillator (2) on the basis of a comparison between a reference signal and a signal dependent on said third frequency; wherein the synthesizer is configured so that said first output (10, 12) provides said target frequency output signal.

Abstract: An integrated oscillator circuit comprises an oscillator configured to be switched between a first frequency and a second frequency. A switching circuit receives an input representing a target frequency and switches the oscillator between the first and second frequencies at intervals determined by the input, so as to cause the average output frequency of the oscillator to approximate the target frequency.

Abstract: An integrated oscillator circuit comprises an oscillator configured to be switched between a first frequency and a second frequency. A switching circuit receives an input representing a target frequency and switches the oscillator between the first and second frequencies at intervals determined by the input, so as to cause the average output frequency of the oscillator to approximate the target frequency.

Abstract: An integrated oscillator circuit comprises an oscillator configured to be switched between a first frequency and a second frequency. A switching circuit receives an input representing a target frequency and switches the oscillator between the first and second frequencies at intervals determined by the input, so as to cause the average output frequency of the oscillator to approximate the target frequency.

Abstract: A temperature sensing device for an integrated circuit comprises an oscillator (2) having a characteristic frequency dependent on the temperature and a digital counter (16) arranged to count a number of pulses generated by the oscillator (2) in a given time interval, or the time taken for the oscillator to generate a given number of pulses. Either of these gives a measured value. The device is configured to use a difference between the measured value and a stored reference value in a linearisation algorithm to estimate a temperature.

Abstract: An integrated-circuit, continuous-time, sigma-delta analog-to-digital converter has a single-ended analog input, a converter reference input, and a ground connection. The converter has a resistor-capacitor integrator arranged to receive the single-ended analog input. The integrator comprises a differential amplifier. The converter also has a clocked comparator connected to an output from the integrator, and circuitry arranged so that reference inputs to the amplifier and to the comparator can be maintained at a common voltage derived from the converter reference input.

Abstract: A temperature sensing device for an integrated circuit comprises an oscillator (2) having a characteristic frequency dependent on the temperature and a digital counter (16) arranged to count a number of pulses generated by the oscillator (2) in a given time interval, or the time taken for the oscillator to generate a given number of pulses. Either of these gives a measured value. The device is configured to use a difference between the measured value and a stored reference value in a linearisation algorithm to estimate a temperature.

Abstract: An integrated-circuit, continuous-time, sigma-delta analogue-to-digital converter has a single-ended analogue input, a converter reference input, and a ground connection. The converter has a resistor-capacitor integrator arranged to receive the single-ended analogue input. The integrator comprises a differential amplifier. The converter also has a clocked comparator connected to an output from the integrator, and circuitry arranged so that reference inputs to the amplifier and to the comparator can be maintained at a common voltage derived from the converter reference input.

Abstract: An integrated-circuit, continuous-time, sigma-delta analogue-to-digital converter has a single-ended analogue input, a converter reference input, and a ground connection. The converter has a resistor-capacitor integrator arranged to receive the single-ended analogue input. The integrator comprises a differential amplifier. The converter also has a clocked comparator connected to an output from the integrator, and circuitry arranged so that reference inputs to the amplifier and to the comparator can be maintained at a common voltage derived from the converter reference input.