Patents by Inventor Ola Torudbakken

Ola Torudbakken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11886982
    Abstract: In a data processing system, at least one processing node is configured to perform computations for a multi-stage process whilst at least one other processor performs the load/unload operations required to calculate a subsequent stage of the multi stage process. An exchange of data then occurs between the processing nodes. At a later time, at least one processing node performs calculations using the data loaded from storage, whilst at least one other processor performs the load/unload operations required to calculate a subsequent stage of the multi stage process.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: January 30, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Ola Torudbakken, Lorenzo Cevolani
  • Patent number: 11886934
    Abstract: A data processing system comprising a plurality of processing nodes, each comprising at least one memory configured to store an array of data items, wherein each of the plurality of processing nodes is configured to execute compute instructions during a compute phase and following a precompiled synchronisation barrier, enter at least one exchange phase. During the at least one exchange phase, a series of collective operations are carried out. Each processing node is configured to perform a reduce scatter collective in at least one first dimension. Using the results of the reduce scatter collective, each processing node performs an allreduce in a second dimension. The processing nodes then perform an all-gather collective in the at least one first dimension using the results of the allreduce.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: January 30, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Lorenzo Cevolani, Fabian Tschopp, Ola Torudbakken
  • Patent number: 11886362
    Abstract: A gateway for use in a computing system to interface a host with the subsystem for acting as a work accelerator to the host, the gateway having an streaming engine for controlling the streaming of batches of data into and out of the gateway in response to pre-compiled data exchange synchronisation points attained by the subsystem, wherein the streaming of batches of data is selectively via at least one of an accelerator interface, a data connection interface, a gateway interface and an memory interface, wherein the streaming engine is configured to perform data preparation processing of the batches of data streamed into the gateway prior to said batches of data being streamed out of the gateway, wherein the data preparation processing comprises at least one of: data augmentation; decompression; and decryption.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: January 30, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Ola Torudbakken, Brian Manula
  • Patent number: 11748287
    Abstract: According to an aspect of the invention, there is provided a computer comprising a plurality of interconnected processing nodes arranged in a configuration with multiple stacked layers. Each layer comprises four processing nodes connected by respective links between the processing nodes. In end layers of the stack, the four processing nodes are interconnected in a ring formation by two links between the nodes, the two links adapted to operate simultaneously. Processing nodes in the multiple stacked layers provide four faces, each face comprising multiple layers, each layer comprising a pair of processing nodes. The processing nodes are programmed to operate a configuration to transmit data around embedded one-dimensional rings, each ring formed by processing nodes in two opposing faces.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: September 5, 2023
    Assignee: GRAPHCORE LIMITED
    Inventors: Simon Knowles, Ola Torudbakken, Lars Paul Huse
  • Patent number: 11740946
    Abstract: A gateway in a computing system for interfacing a host with a subsystem for acting as a work accelerator to the host, the gateway having: an accelerator interface for enabling the transfer of batches of data to the subsystem at pre-compiled data exchange synchronisation points attained by the subsystem; a data connection interface for receiving data to be processed from storage; and a gateway interface for connection to a third gateway. The gateway is configured to store a number of credits indicating at least one of: the availability of data for transfer to the subsystem at a pre-compiled data exchange synchronisation point; and the availability of storage for receiving data from the subsystem at a pre-compiled data exchange synchronisation point. The gateway uses these credits to control whether or not synchronisation barrier is passed by transmitting synchronisation requests upstream to the third gateway or simply acknowledging the requests received.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 29, 2023
    Assignee: Graphcore Limited
    Inventors: Ola Tørudbakken, Daniel John Pelham Wilkinson, Brian Manula, Harald Høeg
  • Patent number: 11675633
    Abstract: A system comprising a gateway for interfacing external data sources with one or more accelerators. The gateway comprises a plurality of virtual gateways, each of which is configured to stream data from the external data sources to one or more associated accelerators. The plurality of virtual gateways are each configured to stream data from external data sources so that the data is received at an associated accelerator in response to a synchronisation point being obtained by a synchronisation zone. Each of the virtual gateways is assigned a virtual ID so that when data is received at the gateway, data can be delivered to the appropriate gateway.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: June 13, 2023
    Assignee: GRAPHCORE LIMITED
    Inventors: Brian Manula, Harald Hoeg, Ola Torudbakken
  • Patent number: 11615038
    Abstract: A gateway for use in a computing system to interface a host with the subsystem for acting as a work accelerator to the host, the gateway having: an accelerator interface for connection to the subsystem to enable transfer of batches of data between the subsystem and the gateway; a data connection interface for connection to external storage for exchanging data between the gateway and storage; a gateway interface for connection to at least one second gateway; a memory interface connected to a local memory associated with the gateway; and a streaming engine for controlling the streaming of batches of data into and out of the gateway in response to pre-compiled data exchange synchronisation points attained by the subsystem, wherein the streaming of batches of data are selectively via at least one of the accelerator interface, data connection interface, gateway interface and memory interface.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: March 28, 2023
    Assignee: Graphcore Limited
    Inventors: Ola Tørudbakken, Brian Manula, Harald Høeg
  • Publication number: 20230054059
    Abstract: A gateway for interfacing a host with a subsystem for acting as a work accelerator to the host. The gateway enables the transfer of batches of data to the subsystem at precompiled data exchange synchronisation points. The gateway acts to route data between accelerators which are connected in a scaled system of multiple gateways and accelerators using a global address space set up at compile time of an application to run on the computer system.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 23, 2023
    Inventors: Ola Torudbakken, Daniel John Pelham Wilkinson, Brian Manula
  • Patent number: 11477050
    Abstract: A gateway for interfacing a host with a subsystem for acting as a work accelerator to the host. The gateway enables the transfer of batches of data to the subsystem at precompiled data exchange synchronisation points. The gateway acts to route data between accelerators which are connected in a scaled system of multiple gateways and accelerators using a global address space set up at compile time of an application to run on the computer system.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 18, 2022
    Assignee: Graphcore Limited
    Inventors: Ola Tørudbakken, Daniel John Pelham Wilkinson, Brian Manula
  • Patent number: 11455155
    Abstract: A computer system comprises a work accelerator, a gateway the transfer of data to the accelerator from external storage, the accelerator executes a first compiled code sequence to perform computations on data transferred to the accelerator from the gateway. The first compiled code sequence comprises a synchronisation instruction indicating a barrier between a compute phase in which the compute instructions are executed and an exchange phase, wherein execution of the synchronisation instruction causes an indication of a pre-compiled data exchange synchronisation point to be transferred to the gateway. The gateway comprises a streaming engine storing a second compiled code sequence in the form of a set of data transfer instructions executable by the streaming engine to perform data transfer operations to stream data through the gateway in the exchange phase, wherein the first and second compiled code sequences are generated as a related set at compile time.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: September 27, 2022
    Assignee: GRAPHCORE LIMITED
    Inventors: Ola Torudbakken, Daniel John Pelham Wilkinson, Brian Manula, Harald Hoeg
  • Publication number: 20220197722
    Abstract: A system comprising a gateway for interfacing external data sources with one or more accelerators. The gateway comprises a plurality of virtual gateways, each of which is configured to stream data from the external data sources to one or more associated accelerators. The plurality of virtual gateways are each configured to stream data from external data sources so that the data is received at an associated accelerator in response to a synchronisation point being obtained by a synchronisation zone. Each of the virtual gateways is assigned a virtual ID so that when data is received at the gateway, data can be delivered to the appropriate gateway.
    Type: Application
    Filed: March 10, 2022
    Publication date: June 23, 2022
    Inventors: Brian MANULA, Harald Hoeg, Ola TORUDBAKKEN
  • Patent number: 11281506
    Abstract: A system comprising a gateway for interfacing external data sources with one or more accelerators. The gateway comprises a plurality of virtual gateways, each of which is configured to stream data from the external data sources to one or more associated accelerators. The plurality of virtual gateways are each configured to stream data from external data sources so that the data is received at an associated accelerator in response to a synchronisation point being obtained by a synchronisation zone. Each of the virtual gateways is assigned a virtual ID so that when data is received at the gateway, data can be delivered to the appropriate gateway.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: March 22, 2022
    Assignee: GRAPHCORE LIMITED
    Inventors: Brian Manula, Harald Hoeg, Ola Torudbakken
  • Patent number: 11237882
    Abstract: A gateway for interfacing a host with a subsystem for acting as a work accelerator to the host. The gateway enables the transfer of batches of data to the subsystem at precompiled data exchange synchronisation points. The gateway comprises a streaming engine having a data mover engine and a memory management engine, the data mover engine and memory management engine being configured to execute instructions in coordination from work descriptors. The memory management engine is configured to execute instructions from the work descriptor to transfer data between external storage and the local memory associated with the gateway. The data mover engine is configured to execute instructions from the work descriptor to transfer data between the local memory associated with the gateway and the subsystem.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 1, 2022
    Assignee: Graphcore Limited
    Inventors: Ola Tørudbakken, Daniel John Pelham Wilkinson, Richard Luke Southwell Osborne, Brian Manula, Harald Høeg
  • Publication number: 20220019487
    Abstract: A host system compiles a set of local programs which are provided over a network to a plurality of subsystems. By defining the synchronisation activity on the host, and then providing that information to the subsystems, the host can service a large number of subsystems. The defined synchronisation activity includes defining the synchronisation groups between which synchronisation barriers occur and the points during program execution at which data exchange with the host occurs. Defining synchronisation activity between the subsystems allows a large number of subsystems to be connecting whilst minimising the required exchanges with the host.
    Type: Application
    Filed: June 4, 2021
    Publication date: January 20, 2022
    Inventors: Ola TORUDBAKKEN, Wei-Lin GUAY
  • Publication number: 20210357340
    Abstract: A gateway for use in a computing system to interface a host with the subsystem for acting as a work accelerator to the host, the gateway having an streaming engine for controlling the streaming of batches of data into and out of the gateway in response to pre-compiled data exchange synchronisation points attained by the subsystem, wherein the streaming of batches of data is selectively via at least one of an accelerator interface, a data connection interface, a gateway interface and an memory interface, wherein the streaming engine is configured to perform data preparation processing of the batches of data streamed into the gateway prior to said batches of data being streamed out of the gateway, wherein the data preparation processing comprises at least one of: data augmentation; decompression; and decryption.
    Type: Application
    Filed: May 27, 2021
    Publication date: November 18, 2021
    Inventors: Ola TORUDBAKKEN, Brian MANULA
  • Patent number: 11169956
    Abstract: One aspect of the invention provides a computer comprising a plurality of interconnected processing nodes arranged in a ladder configuration comprising a plurality of facing pairs of processing nodes. The processing nodes of each pair are connected to each other by two links. A processing node in each pair is connected to a corresponding processing node in an adjacent pair by at least one link. The processing nodes are programmed to operate the ladder configuration to transmit data around two embedded one-dimensional rings formed by respective sets of processing nodes and links, each ring using all processing nodes in the ladder once only.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: November 9, 2021
    Assignee: GRAPHCORE LIMITED
    Inventors: Simon Knowles, Ola Torudbakken, Stephen Felix, Lars Paul Huse
  • Publication number: 20210311808
    Abstract: A data processing system comprising a plurality of processing nodes, each comprising at least one memory configured to store an array of data items, wherein each of the plurality of processing nodes is configured to execute compute instructions during a compute phase and following a precompiled synchronisation barrier, enter at least one exchange phase. During the at least one exchange phase, a series of collective operations are carried out. Each processing node is configured to perform a reduce scatter collective in at least one first dimension. Using the results of the reduce scatter collective, each processing node performs an allreduce in a second dimension. The processing nodes then perform an all-gather collective in the at least one first dimension using the results of the allreduce.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 7, 2021
    Inventors: Lorenzo CEVOLANI, Fabian TSCHOPP, Ola TORUDBAKKEN
  • Publication number: 20210312268
    Abstract: In a data processing system, at least one processing node is configured to perform computations for a multi-stage process whilst at least one other processor performs the load/unload operations required to calculate a subsequent stage of the multi stage process. An exchange of data then occurs between the processing nodes. At a later time, at least one processing node performs calculations using the data loaded from storage, whilst at least one other processor performs the load/unload operations required to calculate a subsequent stage of the multi stage process.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 7, 2021
    Inventors: Ola TORUDBAKKEN, Lorenzo CEVOLANI
  • Publication number: 20210311807
    Abstract: A data processing system comprising a plurality of processing nodes that are arranged to update a model in a parallel manner Each of the processing nodes starts with a different set of updates to model parameters. Each of the processing nodes is configured to perform one or more reduce-scatter collectives so as to exchange and reduce the updates. Having done so, each processing node is configured to apply the reduced set of updates to obtain an updated set of model parameters. The processing nodes then exchange the updated model parameters using an all-gather so that each processing node ends up with the same model parameters at the end of the process.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 7, 2021
    Inventors: Ola TORUDBAKKEN, Lorenzo CEVOLANI
  • Patent number: 11119952
    Abstract: A gateway for use in a computing system to interface a host with the subsystem for acting as a work accelerator to the host, the gateway having an streaming engine for controlling the streaming of batches of data into and out of the gateway in response to pre-compiled data exchange synchronisation points attained by the subsystem, wherein the streaming of batches of data is selectively via at least one of an accelerator interface, a data connection interface, a gateway interface and an memory interface, wherein the streaming engine is configured to perform data preparation processing of the batches of data streamed into the gateway prior to said batches of data being streamed out of the gateway, wherein the data preparation processing comprises at least one of: data augmentation; decompression; and decryption.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: September 14, 2021
    Assignee: GRAPHCORE LIMITED
    Inventors: Ola Torudbakken, Brian Manula