Abstract: A device includes a transmitter to transmit serialized data within a differential direct-current (DC) signal over a differential output line, a multiplexer circuit coupled to the transmitter, and a calibration circuit coupled between the differential output line, a multi-phase clock, and the multiplexer circuit. The multiplexer circuit is to select the serialized data from ones of multiple input lines according to a multi-phase clock and pass the selected serialized data to the transmitter. The serialized data includes a calibration bit pattern. The calibration circuit is to capture and digitize the differential DC signal into a digital stream, measure an error value from the digital stream that is associated with distortion based on the calibration bit pattern, convert the error value into a gradient value, and correct one or more phases of the multi-phase clock to compensate for the distortion based on the gradient value.

Abstract: This disclosure relates to a receiver that includes a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

Abstract: This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

Abstract: This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

Abstract: Injection locked oscillation circuits are applied along clock distribution circuit paths to increase clock signal bandwidth, reduce duty cycle error, reduce quadrature phase error, reduce clock signal jitter, and reduce clock signal power consumption.

Abstract: A circuit includes a chopper switch to receive an analog input signal and output a first chopped signal of a first polarity during a first clock phase and a second chopped signal of a second polarity during a second clock phase. An analog block receives and processes the first and second chopped signals and outputs first and second processed signals, respectively. The analog bock has a first offset voltage associated thereto. The first and second processed signals, each includes a first offset component that is associated with the first offset voltage. A data converter receives and converts the first and second processed signals into first and second digital codes, respectively. An offset canceller receives the first and second digital codes. The offset canceller is configured to remove the first offset components from the first and second digital codes and output a digital output signal corresponding to the analog input signal.

Abstract: An analog-to-digital converter having N comparators is provided. Each one of the N comparators receives a common analog input signal at a corresponding first input, and each one of the N comparators provides an output representing one bit of an N-bit digital conversion of the common analog input signal. The analog-to-digital converter generates the N-bit digital conversion of the common analog input signal without using a reference clock.