Abstract: Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.

Abstract: Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.

Abstract: A test structure for resistive open detection using voltage contrast (VC) inspection and method for using such structure are disclosed. The test structure may include a comparator within the IC chip for comparing a resistance value of a resistive element under test to a reference resistance and outputting a result of the comparing that indicates whether the resistive open exists in the resistive element under test, wherein the result is detectable by the voltage contrast inspection.

Abstract: Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.

Abstract: Structure and methods of determining the complete location of a buried short using voltage contrast inspection are disclosed. In one embodiment, a method includes providing a test structure having a PN junction thereunder; and using the PN junction to determine the location of the buried short using voltage contrast (VC) inspection. A test structure may include a plurality of test elements each having a PN junction thereunder, wherein a location of the buried short within the test structure can be determined using the PN junction and the VC inspection. The PN junction forces a change in illumination brightness of a test element including the buried short, thus allowing determination of the complete location of a buried short.

Abstract: Test structures and a method for voltage contrast (VC) inspection are disclosed. In one embodiment, the test structure includes: a gate stack that is grounded by a ground to maintain the gate stack in an off state during VC inspection, which allows NFET defect detection using VC inspection prior to contact dielectric deposition. The test structure may alternatively include a gate stack that is biased by a bias to maintain the gate stack in an on state during VC inspection. The method may detect source-to-drain shorts in a transistor using VC inspection by providing a gate stack over a source and drain region of the transistor that is grounded by a ground to maintain the gate stack in an off state during VC inspection; and inspecting the transistor using voltage contrast. If the drain of the NFET brightens during VC inspection, this indicates a source to drain short.

Abstract: Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.

Abstract: A method and computer program product for implementing inspection recipe services are provided. The method includes defining a modified reticle pitch for use in inspecting programmed defects on a test structure, the modified reticle pitch extending the distance of one reticle field plus a portion of an adjacent reticle field on the test structure. The test structure includes a number of arrays linearly arranged on the test structure and spaced equidistant, and each of the arrays corresponds to a reticle field and includes a number of cells. The method also includes using the modified reticle field pitch and an alignment site on the test structure to perform a random mode inspection of the test structure.

Abstract: Embodiments of the present invention provide a test structure for inspection of integrated circuits. The test structure may be fabricated on a semiconductor wafer together with one or more integrated circuits. The test structure may include a common reference point for voltage reference; a plurality of voltage dropping devices being connected to the common reference point; and a plurality of electron-collecting pads being connected, respectively, to a plurality of contact points of the plurality of voltage dropping devices. A brightness shown by the plurality of electron-collecting pads during an inspection of the integrated circuits may be associated with a pre-determined voltage.

Abstract: A method, apparatus, and computer program product for implementing inspection recipe services are provided. The apparatus includes a test structure including a semiconductor substrate and a number of arrays disposed on the semiconductor substrate. The arrays are linearly arranged and spaced equidistant. Each of the arrays corresponds to a reticle field and includes a number of cells. The test structure also includes a defect programmed into every third array. The defect is programmed in the same location on each third array. The test structure further includes an alignment site defined on the test structure for providing a point of reference upon inspection. The alignment site, in conjunction with a modified reticle pitch extending the distance of one reticle field plus a portion of an adjacent reticle field, are used to perform a random mode inspection of selected arrays in the test structure.

Abstract: A method, apparatus, and computer program product for implementing inspection recipe services are provided. The apparatus includes a test structure including a semiconductor substrate and a number of arrays disposed on the semiconductor substrate. The arrays are linearly arranged and spaced equidistant. Each of the arrays corresponds to a reticle field and includes a number of cells. The test structure also includes a defect programmed into every third array. The defect is programmed in the same location on each third array. The test structure further includes an alignment site defined on the test structure for providing a point of reference upon inspection. The alignment site, in conjunction with a modified reticle pitch extending the distance of one reticle field plus a portion of an adjacent reticle field, are used to perform a random mode inspection of selected arrays in the test structure.

Abstract: A multi-featured control system which improves the manufacturing capability of the thin-film semiconductor growth process. This system improves repeatability and accuracy of the process, reduces the manpower requirements to operate MBE, and improves the MBE environment for scientific investigation. This system has three levels of feedback control. The first level improves the precision and tracking of the process variables, flux, and substrate temperature. The second level comprises an expert system that uses sensors to monitor the status of the product in order to tailor the process plan in real time so that the exact qualities desired are achieved. The third level features a continuously evolving neural network model of the process which is used to recommend the recipe and command inputs to achieve a desired goal. The third level is particularly useful during the development process for new materials.