Abstract: A semiconductor memory cell includes a semiconductor substrate that defines a trench having trench walls. The semiconductor memory cell also includes a floating gate electrode positioned within the trench and insulated from the trench walls by a first insulation region; a control gate electrode surrounding the trench; and a second insulation layer on the surface of the semiconductor substrate. The semiconductor memory cell further includes a conductive layer positioned on the second insulation layer. The conductive layer includes a channel region positioned above the floating gate electrode. The semiconductor memory cell also includes a source region and a drain region. The source region and the drain region are each formed in the conductive layer. The source region and the drain region are also connected to the channel region.

Abstract: A method for fabricating embedded nonvolatile semiconductor memory cells is described. The method includes forming a first insulating layer on a substrate having a high-voltage region, a memory region and a logic region. The first insulating layer is removed in the memory region, and a second insulating layer is formed. A charge-storing layer is formed and patterned along with a third insulating layer. The first to third insulating layers and also the charge-storing layer are removed in the logic region. A fourth insulating layer is formed and a conductive control layer is formed and patterned.

Abstract: The present invention provides a semiconductor memory cell having a semiconductor substrate (1); a trench (5) provided in the semiconductor substrate (1); a floating gate electrode (45) introduced in the trench (5), which electrode is insulated from the trench walls by a first insulation layer (50); a control gate electrode (80) provided in the semiconductor substrate (1) around the trench (5); a second insulation layer (10) provided on the surface of the semiconductor substrate (1); a conductive layer (20) provided on the second insulation layer (10), which conductive layer forms a channel region (35) above the floating gate electrode (45); and a source region (30) and drain region (40) formed in the conductive layer (20) in each case beside the channel region (35). The invention also provides a corresponding fabrication method.

Abstract: The electrical characteristic of a microelectronic circuit configuration that has at least one analog electronic unit is set. In a configuration step, by feeding and/or extracting electrical charge, the analog electronic unit is put into a state which permanently determines the analog electrical characteristics of the unit. In particular, the floating gate of an EEPROM cell is charged up to a freely selectable charge value lying within a continuous range.

Abstract: A method for fabricating embedded nonvolatile semiconductor memory cells is described. The method includes forming a first insulating layer on a substrate having a high-voltage region, a memory region and a logic region. The first insulating layer is removed in the memory region, and a second insulating layer is formed. A charge-storing layer is formed and patterned along with a third insulating layer. The first to third insulating layers and also the charge-storing layer are removed in the logic region. A fourth insulating layer is formed and a conductive control layer is formed and patterned.

Abstract: A process for producing metal-containing layers, in particular metal-containing diffusion barriers, contact layers and/or antireflection layers. The process according to the invention has a first step in which a metal layer having a predetermined thickness at an elevated temperature is applied to a semiconductor structure. Next, the metal layer is cooled in a nitrogen-containing atmosphere, resulting in a metal nitride layer being formed.

Abstract: The electrical characteristics of a microelectronic circuit configuration that has at least one analog electronic unit is set. In a configuration step, by feeding and/or extracting electrical charge, the analog electronic unit is put into a state which permanently determines the analog electrical characteristics of the unit. In particular, the floating gate of an EEPROM cell is charged up to a freely selectable charge value lying within a continuous range.