Abstract: A driver includes a low-resistance charging path between a supply voltage rail and a first output node, a high-resistance charging path between the supply voltage rail and the first output node, an inverter coupled to the first output node and configured to enable and disable the low-resistance charging path, and a high-resistance discharging path between the first output node and a second output node. The first output node is coupled to a control terminal of a pass gate transistor in some implementations. The low-resistance charging path charges a voltage on the first output node to a threshold voltage of the pass gate transistor, and the high-resistance charging path charges the voltage on the first output node greater than the threshold voltage of the pass gate transistor. The high-resistance discharging path discharges the voltage on the first output node.

Abstract: A driver includes a low-resistance charging path between a supply voltage rail and a first output node, a high-resistance charging path between the supply voltage rail and the first output node, an inverter coupled to the first output node and configured to enable and disable the low-resistance charging path, and a high-resistance discharging path between the first output node and a second output node. The first output node is coupled to a control terminal of a pass gate transistor in some implementations. The low-resistance charging path charges a voltage on the first output node to a threshold voltage of the pass gate transistor, and the high-resistance charging path charges the voltage on the first output node greater than the threshold voltage of the pass gate transistor. The high-resistance discharging path discharges the voltage on the first output node.

Abstract: A driver includes a low-resistance charging path between a supply voltage rail and a first output node, a high-resistance charging path between the supply voltage rail and the first output node, an inverter coupled to the first output node and configured to enable and disable the low-resistance charging path, and a high-resistance discharging path between the first output node and a second output node. The first output node is coupled to a control terminal of a pass gate transistor in some implementations. The low-resistance charging path charges a voltage on the first output node to a threshold voltage of the pass gate transistor, and the high-resistance charging path charges the voltage on the first output node greater than the threshold voltage of the pass gate transistor. The high-resistance discharging path discharges the voltage on the first output node.

Abstract: An electronic device comprising a first node to be coupled to a first antenna, a second node coupled to a second antenna, a third node to be coupled to a third antenna, a first comparator coupled with a first input to the first node and with a second input to a second node, a second comparator coupled with a first input to the first node and with a second input to the third node, a third comparator coupled with a first input to the second node and with a second input to the third node. Each of the first, the second and the third comparators are configured to compare a first current and a second current at the first input and the second input.

Abstract: An electronic device is provided that is adapted to generate a supply voltage at an input node from a radio frequency (RF) signal. The electronic device includes a limiter coupled to the input node for limiting a supply voltage level at the input node that is generated by the received RF signal. The limiter is configured to draw a limiter current from the input node so as to limit the supply voltage level to a maximum and a magnitude of the limiter current is used for controlling a power consumption of the electronic device.

Abstract: An electronic device is provided, which includes a current supplying stage which is adapted to supply a first compensation current and a second compensation current to a first wire or a second wire, wherein the first compensation current is determined during a first clock period, when the first wire and the second wire are connected. The second compensation current is determined during a second clock period while the first wire and the second wire are not connected and the magnitude of the second current represents a ratio of a resistance value of the first wire and a resistance value of the second wire.

Abstract: An electronic device comprising a first node to be coupled to a first antenna, a second node coupled to a second antenna, a third node to be coupled to a third antenna, a first comparator coupled with a first input to the first node and with a second input to a second node, a second comparator coupled with a first input to the first node and with a second input to the third node, a third comparator coupled with a first input to the second node and with a second input to the third node. Each of the first, the second and the third comparators are configured to compare a first current and a second current at the first input and the second input.

Abstract: An ASK demodulator for use in an RFID transponder having a limiter circuit associated with the antenna circuit and converting the ASK antenna field strength modulation into an ASK limiter current modulation by limiting the antenna voltage to a fixed value and thereby causing the limiter current to be substantially proportional to the ASK antenna field strength, and a current discriminator circuit that discriminates the ASK limiter current modulation. By converting the field strength modulation into a proportional limiter current and discriminating that limiter current, a linear relationship and a stable demodulator sensitivity are achieved. The current discrimination can be made accurately under low-voltage conditions.

Abstract: An electronic device is provided that is adapted to generate a supply voltage at an input node from a radio frequency (RF) signal. The electronic device includes a limiter coupled to the input node for limiting a supply voltage level at the input node that is generated by the received RF signal. The limiter is configured to draw a limiter current from the input node so as to limit the supply voltage level to a maximum and a magnitude of the limiter current is used for controlling a power consumption of the electronic device.

Abstract: An electronic device is provided, which includes a current supplying stage which is adapted to supply a first compensation current and a second compensation current to a first wire or a second wire, wherein the first compensation current is determined during a first clock period, when the first wire and the second wire are connected. The second compensation current is determined during a second clock period while the first wire and the second wire are not connected and the magnitude of the second current represents a ratio of a resistance value of the first wire and a resistance value of the second wire.

Abstract: A method of capacitance-to-voltage conversion with an external sensor capacitor (CP) and a capacitance-to-voltage converter (14) implemented on an integrated readout circuit that includes a reference capacitor (CR), a sampling capacitor (CS) and a sampling amplifier (22) and which has input terminals (16) to which the sensor capacitor (CP) is connected. The method comprises the steps of a) applying a reference voltage (Vref) to the series connected sensor capacitor (CP) and reference capacitor (CR) and charging the sampling capacitor (CS) to the potential at the interconnection node (A) between the sensor capacitor (CP) and the reference capacitor (CR), b) connecting the sampling capacitor (CS) to inputs of the sampling amplifier.

Abstract: An apparatus for reading out a differential capacity with a first and second partial capacity includes a first oscillator having a first frequency-determining element connectable to the first partial capacity and a second oscillator having a second frequency-determining element connectable to the second partial capacity; a switching means to switch the first frequency-determining element into a first state or to switch it into a second state, and to switch the second frequency-determining element into a third state or to switch it into a fourth state; read apparatus having a first detection means connected to the first oscillator; and an evaluation means which carries out a quotient formation to obtain a value indicating a quotient of the first and the second partial capacity.

Abstract: A method of capacitance-to-voltage conversion with an external sensor capacitor (CP) and a capacitance-to-voltage converter (14) implemented on an integrated readout circuit that includes a reference capacitor (CR), a sampling capacitor (CS) and a sampling amplifier (22) and which has input terminals (16) to which the sensor capacitor (CP) is connected. The method comprises the steps of a) applying a reference voltage (Vref) to the series connected sensor capacitor (CP) and reference capacitor (CR) and charging the sampling capacitor (CS) to the potential at the interconnection node (A) between the sensor capacitor (CP) and the reference capacitor (CR), b) connecting the sampling capacitor (CS) to inputs of the sampling amplifier.

Abstract: An apparatus for reading out a differential capacity with a first and second partial capacity includes a first oscillator having a first frequency-determining element connectable to the first partial capacity. The apparatus further has a second oscillator having a second frequency-determining element connectable to the second partial capacity. Furthermore, a switching means is provided which is formed to switch the first frequency-determining element into a first state, so that the first oscillator has a first oscillation with a first period duration, or to switch it into a second state, so that the first oscillator has a second oscillation with a second period duration. The switching means is further formed to switch the second frequency-determining element into a third state, so that the second oscillator has a third oscillation with a third period duration, or to switch it into a fourth state, so that the second oscillator has a fourth oscillation with a fourth period duration.

Abstract: A device for determining the viewing direction relative to a fixed reference co-ordinate system comprises a detector for detecting electrooculograms so as to detect the viewing direction of the eyes of a user relative to the user's head. Furthermore, an inertial navigation system is provided for detecting the position of the head relative to said fixed reference co-ordinate system. Finally, the device comprises a computation unit for determining the viewing direction of the eyes of the user relative to said fixed reference co-ordinate system from the detected viewing direction of the eyes relative to the head and from the detected position of the head relative to said fixed reference co-ordinate system.