Abstract: The user interface contains a project window (9, 90, FIGS.2, 3) for interfaces (clips) of a programmable controller and programming windows (20, FIGS. 4, 10, 13; 67, FIG. 16) for each output interface of the programmable controller. Each such programming window (20, 67) contains a base node as a first graphical operating element (21, FIG. 10; 68, FIG. 16) for the output interface of the particular programming window and at least one additional node which serves as a graphical operating element (35, 47, 49, 51, 53, FIG. 10) for another interface (clip) or for a group of linked interfaces of the programmable controller. Each node has an output branch line (44, 48, 50, 52, 54, FIG. 10), the end of which can be routed to the base node or to another node be means of an operating means, such as a mouse. After the end of the output branch line is deposited on a respective other node, both a graphical link between the nodes and a control-system link between the interfaces which the nodes represent (FIG.

Abstract: The user interface contains a project window (9, 90, FIGS. 2, 3) for interfaces (clips) of a programmable controller and programming windows (20, FIGS. 4, 10, 13; 67, FIG. 16) for each output interface of the programmable controller. Each such programming window (20, 67) contains a base node as a first graphical operating element (21, FIG. 10; 68, FIG. 16) for the output interface of the particular programming window and at least one additional node which serves as a graphical operating element (35, 47, 49, 51, 53, FIG. 13) for another interface (clip) or for a group of linked interfaces of the programmable controller. Each node has an output branch line (44, 48, 50, 52, 54, FIG. 13), the end of which can be routed to the base node or to another node by means of an operating means, such as a mouse. After the end of the output branch line is deposited on a respective other node, both a graphical link between the nodes and a controlsystem link between the interfaces which the nodes represent (FIGS.

Abstract: A circuit configuration for storing data has a first clocked register structure connected in parallel with a second register structure. The second register structure is operated in a push-pull mode relative to the first register structure. As a result, changes in the state of an input signal at the input are stored for each clock phase of a clock signal. Therefore, the clocking of the input signal of the circuit configuration can be done at the clock rate of the clock signal.

Abstract: A multiplication circuit for binary coded numbers uses rows of adders and multipliers for parallel computation. Sign bit supplementation is used in which sign bits are supplemented by binary digits in the rows of adders. In particular, the required addition of the sign bit first occurs in the first multiplier row where elements representing simple loads are used in place of adders with inputs that represent multiple input loads. Wiring simplification also is applied in the higher order adders of subsequent adder rows. Circuit simplification is achieved by replacing half adders with inverters.