Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A system to localize a micro-device inside a target body part, including: a micro-device remotely steered and controlled from outside the target body part, a control unit including a memory for storing one ultrasound image of the target body part, one probe being brought in contact with a securing body part of the patient, and at least one tracker connected to the micro-device. The probe and the tracker communicate with ultrasounds, the control unit being thus able to localize, in real time, the tracker within an internal referential defined with regards to the probe, and the control unit displays, on a screen, the ultrasound image and displays, in real time, the localization of the micro-device on the ultrasound image.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A method of generating waveforms of a circuit design in a hardware emulation system, includes, capturing, using a first block of the system, input signals at each k*d emulation cycle, wherein k and d are integers and k?0 and d>0; capturing, using the first logic block at each (k*d+i) cycle, value of each input signal determined to have changed relative to a previous emulation cycle, wherein 0<i<d; capturing, using a second logic block, outputs of sequential elements at each k*w*d emulation cycle, wherein w is an integer greater than zero; capturing, using the second logic block, at each (k*w*d+j*d) emulation cycle, outputs of each sequential element that is determined to have changed relative to cycle (k*w*d+(j?1)*d), wherein j is an integer and wherein 0<j<w; and generating waveforms for the signals based on the captured input signals and captured values of the sequential elements.

Abstract: A circuit hardware emulation module is configured to identify oscillating subgraphs of an emulated graph, or to identify state-holding subgraphs of an emulated graph. The emulation module identifies one or more loops within an emulated circuit; generates an acyclic emulation of at least a portion of the emulated circuit, wherein the acyclic emulation is characterized by one or more loop breakers; generates a loop detector emulation of a hardware-based loop detector circuit based at least in part on a quantity of loop breakers n characterizing the acyclic emulation, wherein the loop detector emulation comprises at least one of an oscillation detector or a state-holding detector; and executes the loop detector emulation for a plurality of input values for the emulated circuit to generate an output indicating at least one of an oscillation status or a state-holding status of the emulated circuit.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: An example is a method. A design of an integrated circuit is loaded onto an emulation system and is emulated by the emulation system. A sequence of frames is captured, by the emulation system, from the emulation. The sequence of frames includes frame intervals, and each frame interval includes a full frame and a delta primary frame subsequent to the full frame. The full frame is captured at a respective sample time, and the full frame includes signals of the design or a change of the signals relative to a respective sample time of the full frame of a previous frame interval. The delta primary frame is captured at a respective sample time, and the delta primary frame includes a change of a subset of the signals relative to a respective sample time of a previous frame of the respective frame interval. The sequence of frames is stored to memory.

Abstract: A circuit hardware emulation module is configured to identify oscillating subgraphs of an emulated graph, or to identify state-holding subgraphs of an emulated graph. The emulation module identifies one or more loops within an emulated circuit; generates an acyclic emulation of at least a portion of the emulated circuit, wherein the acyclic emulation is characterized by one or more loop breakers; generates a loop detector emulation of a hardware-based loop detector circuit based at least in part on a quantity of loop breakers n characterizing the acyclic emulation, wherein the loop detector emulation comprises at least one of an oscillation detector or a state-holding detector; and executes the loop detector emulation for a plurality of input values for the emulated circuit to generate an output indicating at least one of an oscillation status or a state-holding status of the emulated circuit.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: The invention relates to a method that makes it possible to automatically and exactly calculate the probabilities associated with a Boolean function. The probability of an event represented by a Boolean function (f) is determined by constituting a binary decision diagram of the function and by making recursive traversals through the diagram.

Abstract: The invention provides a method for automatically producing, in a memory zone of a data-processing device, an implicit representation of the prime implicants of a Boolean function, using that device. A Boolean function is represented, in another memory zone of that device, in the form of a binary decision diagram (f) of that function. The implicit representation is obtained from the decision diagram, by taking recursive paths across that diagram to find intermediate elements, which are then combined after each recursion. Each intermediate element uses occurrence variables (O.sub.1, . . . ,O.sub.n) and sign variables (S.sub.1, . . . ,S.sub.n). Means are used to obtain standardized intermediate elements during their creation, thus reducing memory consumption, and means of combining the intermediate elements after their standardization.