Abstract: The invention concerns a method for fabricating a damascene type structure of interconnections on a semiconductor device. It includes the following steps: formation of a first level of conductors in a first electric insulating layer and of a second level of conductors in a second electric insulating layer, with the conductors in the first level being arranged with a pre-determined spacing in order to allow, in a later step, the formation of air or vacuum gaps between the conductors in the first level, elimination of the second electric insulating layer, elimination, at least partial, of the first electric insulating layer in order to eliminate at least some parts of the first layer corresponding to the gaps to be formed, deposit, over the structure thus obtained, of a material with low permittivity, with this deposit not filling the space between the conductors in the first level whose spacing has been planned to allow the formation of gaps.

Abstract: The invention relates to a process for making a copper connection with a copper connection element in an integrated circuit comprising a damascene structure, with the connection element being covered successively with an encapsulation layer and at least one layer of dielectric material with a very low dielectric constant. The process includes the steps of etching the layer of dielectric material until the encapsulation layer is reached in order to obtain a connection hole opposite the connection element. A protective layer is then formed on the walls of the connection hole, with the protective layer preventing contamination of the dielectric layer from diffusion of copper. The protective and encapsulation layers are then etched at the bottom of the connection hole in such a way as to reveal the connection element. The connection hole is then filled with copper.