Abstract: A low to high voltage level converter includes first and second n-channel transistors arranged to force to the ground voltage a first connection node and a second connection node, respectively. A boosting circuit operates to boost an input voltage of at least one of a first and second control nodes for the first and second n-channel transistors above a low voltage level. The converter further includes first and second cross-coupled p-channel transistors arranged to force to the high voltage level the first connection node and the second connection node, respectively. A digital output signal is taken from one of the first and second connection nodes.

Abstract: A low to high voltage level converter includes first and second n-channel transistors arranged to force to the ground voltage a first connection node and a second connection node, respectively. A boosting circuit operates to boost an input voltage of at least one of a first and second control nodes for the first and second n-channel transistors above a low voltage level. The converter further includes first and second cross-coupled p-channel transistors arranged to force to the high voltage level the first connection node and the second connection node, respectively. A digital output signal is taken from one of the first and second connection nodes.

Abstract: A method is for controlling reading of a dynamic random access memory (DRAM) including memory cells connected to a bit line of a memory plane of the DRAM and associated with a main reference cell connected to a reference bit line. The method may include reading and refreshing the contents of the memory cell and pre-charging the bit line, the reference bit line and the main reference cell for a subsequent read access. During reading and refreshing the memory cell, the main reference cell and a secondary reference cell connected to the bit line may be activated and, after having deactivated the two reference cells, they are pre-charged to a final pre-charge voltage. The final pre-charge voltage may be chosen to be less than or greater than (as a function of the NMOS or PMOS technology used, respectively) half the sum of a high-state storage voltage and a low-state storage voltage.