Abstract: A connector that is configured to receive a smart card includes: a first contact configured to receive a power supply voltage and corresponding to a first (power supply) contact area of the smart card, a second contact configured to receive a reference voltage and corresponding to contact a second (reference voltage) contact area of the smart card, and a third contact corresponding to a three-state (input/output) contact area of the smart card. A first light-emitting diode having an anode coupled to the third contact and a cathode coupled to the second contact. A second light-emitting diode has a cathode coupled to the third contact and an anode coupled to the first contact. Turning on/off of the first and second light-emitting diode is controlled by the smart card through the signal at the three-state (input/output) contact area.

Abstract: A light-emitting diode has an anode terminal coupled to a node of application of a power supply voltage by a first transistor and a cathode terminal coupled to a node of application of a reference voltage by a second transistor. A microcontroller includes a digital-to-analog converter and a comparator, with the comparator having a first input coupled to one of the anode and cathode terminals of the diode and a second input configured to receive an output voltage of the converter. An output signal of the comparator controls one of the first and second transistors to turn off when the comparator detects an operating condition where current flow in the light-emitting diode exceeds maximum current limit (such as with the light-emitting diode operating in an exponential operating area.

Abstract: A smart card includes a first circuit delivering a power supply voltage and a second circuit coupled to the first circuit by an electrical conductor and powered with the power supply voltage. A light-emitting diode has a first terminal coupled to the electrical conductor and a second terminal coupled to a first terminal of the second circuit. During a first operating phase, the first circuit delivers a first value of the power supply voltage and the second circuit applies a first voltage to the first terminal. During a second operating phase, the first circuit delivers a second value of the power supply voltage and the second circuit applies a second voltage to the first terminal.

Abstract: A light-emitting diode has an anode terminal coupled to a node of application of a power supply voltage by a first transistor and a cathode terminal coupled to a node of application of a reference voltage by a second transistor. A microcontroller includes a digital-to-analog converter and a comparator, with the comparator having a first input coupled to one of the anode and cathode terminals of the diode and a second input configured to receive an output voltage of the converter. An output signal of the comparator controls one of the first and second transistors to turn off when the comparator detects an operating condition where current flow in the light-emitting diode exceeds maximum current limit (such as with the light-emitting diode operating in an exponential operating area.

Abstract: A smart card includes a first circuit delivering a power supply voltage and a second circuit coupled to the first circuit by an electrical conductor and powered with the power supply voltage. A light-emitting diode has a first terminal coupled to the electrical conductor and a second terminal coupled to a first terminal of the second circuit. During a first operating phase, the first circuit delivers a first value of the power supply voltage and the second circuit applies a first voltage to the first terminal. During a second operating phase, the first circuit delivers a second value of the power supply voltage and the second circuit applies a second voltage to the first terminal.

Abstract: A connector that is configured to receive a smart card includes: a first contact configured to receive a power supply voltage and corresponding to a first (power supply) contact area of the smart card, a second contact configured to receive a reference voltage and corresponding to contact a second (reference voltage) contact area of the smart card, and a third contact corresponding to a three-state (input/output) contact area of the smart card. A first light-emitting diode having an anode coupled to the third contact and a cathode coupled to the second contact. A second light-emitting diode has a cathode coupled to the third contact and an anode coupled to the first contact. Turning on/off of the first and second light-emitting diode is controlled by the smart card through the signal at the three-state (input/output) contact area.

Abstract: A microcircuit card includes a first (general purpose) microcontroller, a second (secure processing) microcontroller, at least one module of communication with the outside of the card, and a biometric sensor. Any communication with the outside of the card transits through the first microcontroller. Any communication between the sensor and the second microcontroller transits through the first microcontroller. Furthermore, the second microcontroller is not involved in any communication to the outside of the card.

Abstract: An integrated circuit memory comprises a circuit that keeps the column voltage constant during the recording of a binary value. This circuit has a differential amplifier which measures the difference between a reference voltage given by a voltage divider and a voltage representative of the bit line. This amplifier gives a signal that is applied to the gate of a transistor of the column-addressing circuit.

Abstract: An integrated circuit memory comprises a circuit that keeps the column voltage constant during the recording of a binary value. This circuit has a differential amplifier which measures the difference between a reference voltage given by a voltage divider and a voltage representative of the bit line. This amplifier gives a signal that is applied to the gate of a transistor of the column-addressing circuit.

Abstract: A circuit for the detection of current leaks on a bit line of a memory (such as an EPROM or flash EPROM), which includes a current generator and a means to apply zero volts to the gates of all the cells of the bit line. The detection information is delivered by a comparison circuit. It corresponds to the result of the comparison between the test current and the current flowing in the bit line. Advantageously, the detection circuit is incorporated into the read circuit of the memory. Also disclosed is the associated detection method and a memory circuit includes a detection circuit.

Abstract: An integrated circuit memory organized in rows and columns of memory cells and having a plurality of redundancy fuses for storing an address of defective rows and columns of the memory cells, in the redundancy fuses, and for selecting a replacement redundant element when an address of a defective row or column is detected. The address code of each defective row or column is recorded in a column of redundancy fuses, each row of the column comprising two cells per digit of the address code, each cell being responsive to either the digit itself or its complement. During a reading of the integrated circuit, only the column that corresponds to the previously recorded address code will not be characterized by a current flow and will be selected as the associated redundant element.

Abstract: A circuit for the detection of current leaks on a bit line of a memory (such as an EPROM or flash EPROM), which essentially utilizes a current generator and a circuit to apply zero volts to the gates of all the cells of the bit line. The detection information is delivered by a comparison circuit. It corresponds to the result of the comparison between the test current and the current flowing in the bit line. Advantageously, the detection circuit is incorporated into the read circuit of the memory. Also disclosed is the associated detection method and a memory circuit using a detection circuit such as this.

Abstract: A method of checking post-erasure contents of an erasable permanent memory containing an instruction register and an address register, the method including steps of writing an erasure-checking instruction word into the instruction register, and timing-out for a predetermined duration. The step of writing the instruction word to the instruction register also initiates the steps of opening of the address register, presenting a first address to the address register, iteratively reading the contents of the memory at the address indicated by the address register and incrementing the presented address until the entire memory has been checked, and closing the address register. A device for implementing this method includes a circuit for generating an address-transfer enable signal applied to the address register.

Abstract: A circuit for protecting nonvolatile memories against loss of Vcc while Vpp is high. An NMOS gated by Vcc is connected, in series with a load element, between Vpp and ground. The node between the NMOS and the load element gates a PMOS which is interposed between Vpp and the memory. Thus when Vcc fails while Vpp is high, the NMOS will turn off, and the load element will pull up the gate of the PMOS to turn it off, interrupting the Vpp supply. This prevents spurious write or erase operations under these circumstances. The circuit can be designed to trigger at threshold voltages as low as V.sub.TN, and is thus particularly advantageous for operation with specified Vcc values of 3 Volts or less.

Abstract: A method for the programming of a data element in an electrically programmable memory in integrated circuit form comprising a data input/output bus, an address bus, a register for the control of instruction sequencing modes and an enable signal (/OE), said signal enabling the data output bus in an active state. When the control register receives a uniform programming instruction, it sends a uniform programming sequencing mode signal so that an inactive state of the enable signal triggers the programming of the data element at a memory address present in the address bus and so that the active state of the enable signal triggers the stopping of the programming operation. Also disclosed is an electrically programmable memory in integrated circuit form, implementing a method such as this. The disclosure can be applied to electrically programmable memories.

Abstract: A high-voltage switching circuit comprising two arms, wherein each arm has a P-channel load transistor, a forward biased diode and an N-channel switching transistor series-connected between the high voltage and the ground. The gate of the N-channel transistor is controlled by a switching signal C in one arm and by the complementary switching signal C in the other arm. Such a structure enables the stress undergone by the load and switching transistors of the switching circuit to be reduced by several magnitudes.

Abstract: A device for the erasure of sectors of a flash EPROM memory map comprises routing means to apply an erasing voltage to several sectors selected simultaneously by a predetermined resistor for all the sectors. Advantageously, the routing means enable the application of the erasing voltage to a sector selected individually by a resistor proper to the sector.

Abstract: A circuit for the detection of current leaks on a bit line of a memory (such as an EPROM or flash EPROM), which includes a current generator and circuitry for applying zero volts to the gates of all the cells f the bit line. The detection information is delivered by a comparison circuit. It corresponds to the result of the comparison between the test current and the current flowing in the bit line. Advantageously, the detection circuit is incorporated into the read circuit of the memory. Also disclosed is an associated detection method, and a memory circuit which includes such a detection circuit.