Patents by Inventor Olivier Rozeau
Olivier Rozeau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10914703Abstract: Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nw nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps: measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets NW, width WW,i, of the nanowire/nanosheet number i, i being an integer from 1 to NW, thickness of the nanowire/nanosheet HW,i, number i, i being an integer from 1 to NW, corner radius RW,i of the nanowire/nanosheet number i, i being an integer from 1 to NW, RW,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage ?T given by ?T=kBT/q; measuring the total gate capacitance for a plurality of gate voltages; determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowireType: GrantFiled: November 30, 2017Date of Patent: February 9, 2021Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Olivier Rozeau, Marie-Anne Jaud, Joris Lacord, Sébastien Martinie, Thierry Poiroux
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Patent number: 10777701Abstract: A photosensitive transistor device, on a semiconductor on insulator substrate, the photosensitive zone being formed in a substrate support layer and being arranged so that the concentration of photogenerated charges in the photosensitive zone can be increased towards a given zone facing the channel zone of the transistor.Type: GrantFiled: August 28, 2018Date of Patent: September 15, 2020Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Lina Kadura, Laurent Grenouillet, Olivier Rozeau, Alexei Tchelnokov
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Patent number: 10290667Abstract: Photosensitive logic cell on a semiconductor-on-insulator substrate, possessing a P type transistor and an N type transistor fabricated on the front face of the substrate and whose respective threshold voltages can be modulated according to the quantity of photons received by a photosensitive zone provided opposite these transistors, the photosensitive zone possessing a photo-detection region whose arrangement is such that it favours illumination by the face of the photosensitive zone.Type: GrantFiled: October 26, 2016Date of Patent: May 14, 2019Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Olivier Rozeau, Laurent Grenouillet
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Publication number: 20190074398Abstract: A photosensitive transistor device (T1), on a semiconductor on insulator substrate, the photosensitive zone (20) being formed in the substrate support layer and being arranged so that the concentration of photogenerated charges in the photosensitive zone can be increased towards a given zone facing the channel zone of the transistor.Type: ApplicationFiled: August 28, 2018Publication date: March 7, 2019Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Lina Kadura, Laurent Grenouillet, Olivier Rozeau, Alexei Tchelnokov
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Publication number: 20180156749Abstract: Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nw nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps: measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets Nw, width Ww,i, of the nanowire/nanosheet number i, i being an integer from 1 to Nw, thickness of the nanowire/nanosheet Hw,i, number i, i being an integer from 1 to Nw, corner radius Rw,i of the nanowire/nanosheet number i, i being an integer from 1 to Nw, Rw,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage ?T given by ?T=kBT/q; measuring the total gate capacitance for a plurality of gate voltages; determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowireType: ApplicationFiled: November 30, 2017Publication date: June 7, 2018Inventors: Olivier ROZEAU, Marie-Anne JAUD, Joris LACORD, Sébastien MARTINIE, Thierry POIROUX
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Patent number: 9841657Abstract: Photosensitive logic inverter, in particular of the CMOS type, formed of a transistor of type P and of a transistor of type N of which the respective threshold voltages can be modulated according to the quantity of photons received by a photosensitive zone provided opposite these transistors.Type: GrantFiled: May 22, 2015Date of Patent: December 12, 2017Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Laurent Grenouillet, Olivier Rozeau
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Patent number: 9761583Abstract: A method for making connection elements between two different levels of components in a 3D integrated circuit, including: forming a lateral insulating area supported on at least one given conducting area among several interconnection areas on a first level of components, the insulating area extending around a semiconducting layer on a second level in which at least one transistor can be formed; removing a first portion of the lateral insulating area so as to form at least one hole exposing said given conducting area; and depositing a conducting material in the hole so as to form a first electrical connection element between the second component and the given conducting area.Type: GrantFiled: June 8, 2016Date of Patent: September 12, 2017Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Claire Fenouillet-Beranger, Bernard Previtali, Olivier Rozeau
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Publication number: 20170125458Abstract: Photosensitive logic cell on a semiconductor-on-insulator substrate, possessing a P type transistor and an N type transistor fabricated on the front face of the substrate and whose respective threshold voltages can be modulated according to the quantity of photons received by a photosensitive zone provided opposite these transistors, the photosensitive zone possessing a photo-detection region whose arrangement is such that it favours illumination by the face of the photosensitive zone.Type: ApplicationFiled: October 26, 2016Publication date: May 4, 2017Applicant: Commissariat a L'Energie Atomique et aux Energies AlternativesInventors: Olivier ROZEAU, Laurent GRENOUILLET
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Publication number: 20160365342Abstract: Method for making connection elements between two different levels of components in a 3D integrated circuit including steps of: forming a lateral insulating area supported on at least one given conducting area among several interconnection areas on a first level of components, the insulating area extending around a semiconducting layer on a second level in which at least one transistor can be formed, removing a first portion of the lateral insulating area so as to form a first hole exposing said given conducting area; deposit a conducting material in the hole so as to form a first electrical connection element between the second component and said given conducting area.Type: ApplicationFiled: June 8, 2016Publication date: December 15, 2016Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Claire FENOUILLET-BERANGER, Bernard PREVITALI, Olivier ROZEAU
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Publication number: 20160019327Abstract: A computer implemented method for calculating a charge density q1 of a first gate of a double gate transistor comprising a thin body with a first and a second gate interface, the method including determining, using a physical processor, an initial estimate q1,init of the charge density of the first gate; performing, using the physical processor, at least two basic corrections of the initial estimate based on a Taylor development of a function fzero(q1) able to be nullified by a correct value of the charge density q1 of the first gate.Type: ApplicationFiled: July 16, 2014Publication date: January 21, 2016Inventors: Thierry POIROUX, Marie-Anne JAUD, Sebastien MARTINIE, Olivier ROZEAU
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Patent number: 9235668Abstract: A computer implemented method for calculating a charge density q1 of a first gate of a double gate transistor comprising a thin body with a first and a second gate interface, the method including determining, using a physical processor, an initial estimate q1,init of the charge density of the first gate; performing, using the physical processor, at least two basic corrections of the initial estimate based on a Taylor development of a function fzero(q1) able to be nullified by a correct value of the charge density q1 of the first gate.Type: GrantFiled: July 16, 2014Date of Patent: January 12, 2016Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Thierry Poiroux, Marie-Anne Jaud, Sebastien Martinie, Olivier Rozeau
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Publication number: 20150338720Abstract: Photosensitive logic inverter, in particular of the CMOS type, formed of a transistor of type P and of a transistor of type N of which the respective threshold voltages can be modulated according to the quantity of photons received by a photosensitive zone provided opposite these transistors.Type: ApplicationFiled: May 22, 2015Publication date: November 26, 2015Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Laurent GRENOUILLET, Olivier ROZEAU
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Publication number: 20150091089Abstract: A MOS transistor has a gate insulator layer that is made of a material of high dielectric constant deposited on a substrate. The gate insulator layer extends, with a constant thickness, under and beyond a gate stack. Spacers of low dielectric constant are formed on either side of the gate stack and vertically separated from the substrate by the extension of the gate insulator layer beyond the sides of the gate stack. The spacers of low dielectric constant are preferably air spacers.Type: ApplicationFiled: September 29, 2014Publication date: April 2, 2015Applicants: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Heimanu Niebojewski, Yves Morand, Cyrille Le Royer, Olivier Rozeau
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Patent number: 8399316Abstract: A method for making a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least one first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of the double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively; and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least a first implantation selective relative to the first block, the implantation being done on a first side of the given structure, the part of the structure on the other side of the normal to the principal plane of the substrate passing through the semiconducting zone not being implanted.Type: GrantFiled: December 28, 2007Date of Patent: March 19, 2013Assignee: Commissariat a l'Energie AtomiqueInventors: Maud Vinet, Olivier Thomas, Olivier Rozeau, Thierry Poiroux
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Patent number: 8324057Abstract: A method for fabricating a microelectronic device with one or several asymmetric and symmetric double-gate transistors on the same substrate.Type: GrantFiled: December 28, 2007Date of Patent: December 4, 2012Assignee: Commissariat a l'Energie AtomiqueInventors: Maud Vinet, Olivier Thomas, Olivier Rozeau, Thierry Poiroux
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Patent number: 8232168Abstract: A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of said double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block.Type: GrantFiled: December 28, 2007Date of Patent: July 31, 2012Assignee: Commissariat a l'Energie AtomiqueInventors: Maud Vinet, Olivier Thomas, Olivier Rozeau, Thierry Poiroux
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Patent number: 8105906Abstract: A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block.Type: GrantFiled: December 28, 2007Date of Patent: January 31, 2012Assignee: Commissariat a l'Energie AtomiqueInventors: Maud Vinet, Olivier Thomas, Olivier Rozeau, Thierry Poiroux
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Publication number: 20100320541Abstract: A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block.Type: ApplicationFiled: December 28, 2007Publication date: December 23, 2010Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUEInventors: Maud Vinet, Olivier Thomas, Olivier Rozeau, Thierry Poiroux
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Publication number: 20100317167Abstract: A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of said double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block.Type: ApplicationFiled: December 28, 2007Publication date: December 16, 2010Applicant: COMMISSARIAT A L' ENERGIE ATOMIQUEInventors: Maud Vinet, Olivier Thomas, Olivier Rozeau, Thierry Poiroux
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Publication number: 20100178743Abstract: A method for making a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least one first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of the double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively; and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least a first implantation selective relative to the first block, the implantation being done on a first side of the given structure, the part of the structure on the other side of the normal to the principal plane of the substrate passing through the semiconducting zone not being implanted.Type: ApplicationFiled: December 28, 2007Publication date: July 15, 2010Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUEInventors: Maud Vinet, Olivier Thomas, Olivier Rozeau, Thierry Poiroux