Abstract: This asynchronous processor core comprises a loading unit for sequentially loading instruction lines, functional units for executing instructions and a decoder for decoding instruction lines loaded by the loading unit into instructions executable by the functional units. It comprises an execution control module configured as a two-state automaton: a sleep state (S1), wherein the asynchronous processor core awaits an interrupt control signal to execute an interrupt routine; an execution state (S2), wherein the decoder awaits a new interrupt routine instruction line to be decoded. The execution control module additionally manages a state variable (status) of the loading unit to selectively authorize or prevent, according to at least the value of this state variable (status), the loading of a new instruction line.

Abstract: This asynchronous processor core comprises a loading unit for sequentially loading instruction lines, functional units for executing instructions and a decoder for decoding instruction lines loaded by the loading unit into instructions executable by the functional units. It comprises an execution control module configured as a two-state automaton: a sleep state (S1), wherein the asynchronous processor core awaits an interrupt control signal to execute an interrupt routine; an execution state (S2), wherein the decoder awaits a new interrupt routine instruction line to be decoded. The execution control module additionally manages a state variable (status) of the loading unit to selectively authorize or prevent, according to at least the value of this state variable (status), the loading of a new instruction line.

Abstract: A method of programming a FPGA, wherein the FPGA comprises an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network, the method comprises the steps of: providing a high-level configuration file containing: first data defining a set of macrocells and their relative positions; second data defining a configuration of the hardware blocks of the macrocells; and third data defining interconnections between the macrocells; wherein said high-level configuration file contains neither data defining an absolute position of the macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks; converting said high-level configuration file into a bitstream file; and uploading the bitstream file into the FPGA. A semiconductor chip comprising a FPGA and a device configured for programming the FPGA are provided.

Abstract: A method of programming a FPGA, wherein the FPGA comprises an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network, the method comprises the steps of: providing a high-level configuration file containing: first data defining a set of macrocells and their relative positions; second data defining a configuration of the hardware blocks of the macrocells; and third data defining interconnections between the macrocells; wherein said high-level configuration file contains neither data defining an absolute position of the macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks; converting said high-level configuration file into a bitstream file; and uploading the bitstream file into the FPGA. A semiconductor chip comprising a FPGA and a device configured for programming the FPGA are provided.

Abstract: An encoder comprises a first and a second input, and a first and a second output, and the encoder comprises a selection block suitable for selecting a more significant bit and a less significant bit. The encoder comprises a switching block suitable for connecting the first input to the first output, and the second input to the second output, the switching block being suitable for being switched in order to connect the first input to the second output and the second input to the first output, when the selection block has selected a less significant bit and a more significant bit. A decoder, a storage medium and an electronic system is also disclosed.

Abstract: The invention relates to an encoder (2) comprising a first (4) and a second (14) input, and a first (6) and a second (16) output, the encoder (2) comprising a selection block (24, 26, 28) suitable for selecting a more significant bit and a less significant bit. The encoder (2) comprises a switching block (44, 46) suitable for connecting the first input (4) to the first output (6), and the second input (14) to the second output (16), the switching block (44, 46) being suitable for being switched in order to connect the first input (4) to the second output (16) and the second input (14) to the first output (6), when the selection block (24, 26, 28) has selected a less significant bit and a more significant bit. The invention relates also to a decoder, a storage medium and an electronic system.

Abstract: The invention concerns a device for detecting abnormal situations, in particular falls, in a living being, comprising means generating an alarm signal representing an abnormal situation, based on analysis of at least an activity information and, at least in some cases, at least a physiological information.