Patents by Inventor Olivier ZANELLATO
Olivier ZANELLATO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240186195Abstract: An integrated circuit package includes a support substrate having a mounting face and a lateral wall having an inner face and an outer face. The inner face delimits with the mounting face a cavity. The outer face includes a step extending outwardly of the package. An electronic chip disposed in the cavity and electrically connected to electrically-conductive contact pads. A sealing structure is bonded by a glue to an upper face of the lateral wall to seal the cavity. The glue does not spill out over the outer face of the lateral wall. Electrically-conductive connection elements are located over a lower face of the support substrate and electrically cooperate with the contact pads through an interconnection network located in the support substrate.Type: ApplicationFiled: December 5, 2023Publication date: June 6, 2024Applicant: STMicroelectronics International N.V.Inventors: Laurent HERARD, Olivier ZANELLATO, Patrick LAURENT
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Publication number: 20240072214Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Olivier ZANELLATO, Remi BRECHIGNAC, Jerome LOPEZ
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Patent number: 11862757Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.Type: GrantFiled: September 24, 2021Date of Patent: January 2, 2024Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Olivier Zanellato, Remi Brechignac, Jerome Lopez
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Patent number: 11798967Abstract: An integrated circuit package includes a support substrate having a front side and a back side and an optical integrated circuit die having a back side mounted to the front side of the support substrate and having a front side with an optical sensing circuit. A glass optical element die has a back side mounted to the front side of the optical integrated circuit die over the optical sensing circuit. The mounting of the glass optical element die is made by a layer of transparent adhesive which extends to the cover the optical sensing circuit and a portion of the front side of the optical integrated circuit die peripherally surrounding the optical sensing circuit. An encapsulation material body encapsulates the glass optical element die and the optical integrated circuit die.Type: GrantFiled: October 6, 2021Date of Patent: October 24, 2023Assignees: STMicroelectronics Asia Pacific Pte Ltd, STMicroelectronics (Grenoble 2) SASInventors: How Yang Lim, Olivier Zanellato
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Publication number: 20230104584Abstract: An integrated circuit package includes a support substrate having a front side and a back side and an optical integrated circuit die having a back side mounted to the front side of the support substrate and having a front side with an optical sensing circuit. A glass optical element die has a back side mounted to the front side of the optical integrated circuit die over the optical sensing circuit. The mounting of the glass optical element die is made by a layer of transparent adhesive which extends to the cover the optical sensing circuit and a portion of the front side of the optical integrated circuit die peripherally surrounding the optical sensing circuit. An encapsulation material body encapsulates the glass optical element die and the optical integrated circuit die.Type: ApplicationFiled: October 6, 2021Publication date: April 6, 2023Applicants: STMicroelectronics Asia Pacific Pte Ltd, STMicroelectronics (Grenoble 2) SASInventors: How Yang LIM, Olivier ZANELLATO
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Publication number: 20220102591Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.Type: ApplicationFiled: September 24, 2021Publication date: March 31, 2022Applicant: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Olivier ZANELLATO, Remi BRECHIGNAC, Jerome LOPEZ
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Patent number: 11152646Abstract: The present invention relates to a method for producing a microelectronic device, successively including: forming a first current collector on a face of a substrate; forming a first electrode on, and in electrical continuity with, a portion of the first current collector; heat treating the first electrode wherein: forming the first collector comprises forming a first collector layer on the face of the substrate and forming a second collector layer covering at least one part to produce a covered part of the first collector layer and having a first face in contact with the first electrode, the second collector layer is configured to protect the covered part during the heat treating, such that the heat treating does not oxidise the covered part.Type: GrantFiled: December 20, 2018Date of Patent: October 19, 2021Assignee: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Christophe Dubarry, Olivier Zanellato
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Publication number: 20190207263Abstract: The present invention relates to a method for producing a microelectronic device, successively including: forming a first current collector on a face of a substrate; forming a first electrode on, and in electrical continuity with, a portion of the first current collector; heat treating the first electrode wherein: forming the first collector comprises forming a first collector layer on the face of the substrate and forming a second collector layer covering at least one part to produce a covered part of the first collector layer and having a first face in contact with the first electrode, the second collector layer is configured to protect the covered part during the heat treating, such that the heat treating does not oxidise the covered part.Type: ApplicationFiled: December 20, 2018Publication date: July 4, 2019Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Christophe DUBARRY, Olivier ZANELLATO