Abstract: An insulated trench isolation structure is formed by ion implanting impurities proximate to the trench edges for enhancing the oxidation rate and, hence, increasing the thickness of the oxide at the trench edges. Embodiments include ion implanting impurities prior to growing an oxide liner. The resulting thick oxide on the trench edges avoids overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.

Abstract: A semiconductor wafer including an NMOS device and a PMOS device. The NMOS device is formed to have a high-K gate dielectric and the PMOS device is formed to have a standard-K gate dielectric. A method of forming the NMOS device and the PMOS device is also disclosed.

Abstract: An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches.

Abstract: The gate structure of the MOSFET of the present invention is formed to have a longer length toward the top of the gate structure such that a spacer having a substantially rectangular shaped is formed at the sidewalls of the gate structure. For fabricating a gate structure of a field effect transistor on a semiconductor substrate, a layer of gate structure material is deposited on the semiconductor substrate. The composition of the layer of gate structure material is adjusted along a depth of the layer of gate structure material for a slower etch rate toward a top of the layer of gate structure material that is further from the semiconductor substrate. The gate structure is then formed by patterning and etching the layer of gate structure material. The slower etch rate toward the top of the layer of gate structure material results in a longer length toward a top of the gate structure that is further from the semiconductor substrate.

Abstract: Accurate photolighographic processing is achieved employing a stepper global alignment structure enabling formation thereon of a substantially transparent layer having a substantially planar upper surface. Embodiments include a set of global alignment marks comprising spaced apart trenches, each trench segmented into a plurality of narrow trenches spaced apart by uprights and forming a dummy topographical area of narrow trenches surrounding the set of alignment marks. The segmented trenches and the dummy topographical area effectively provide a substantially uniform topography enabling deposition of a transparent layer without steps and effective local planarization. Since the upper surface of the transparent layer is substantially planar, layers of material deposited on the transparent layer during subsequent processing also have a substantially planar upper surface, thereby enabling transmission of the signal produced by the alignment marks to the stepper with minimal distortion.

Abstract: An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate without a planarization mask or etch. Embodiments include forming trenches and refilling them with an insulating material which also covers the substrate surface, followed by polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches. A second layer of insulating material is then deposited to fill seams in the insulating material above the small trenches and to fill steps in the insulating material above the large trenches. The insulating material is then planarized.

Abstract: A method for effectively generating limited trench width isolation structures without incurring the susceptibility to dishing problems to produce high quality ICs employs a computer to generate data representing a trench isolation mask capable of being used to etch a limited trench width isolation structure about the perimeter of active region layers, polygate layers, and Local Interconnect (LI) layers. Once the various layers are defined using data on the computer and configured such that chip real estate is maximized, then the boundaries are combined using, for example, logical OR operators to produce data representing an overall composite layer. Once the data representing the composite layer is determined, the data is expanded evenly outward in all horizontal directions by a predetermined amount, .lambda., to produce data representing a preliminary expanded region.

Abstract: An insulated trench isolation structure is formed by ion implanting impurities proximate the trench edges to enhance the silicon oxidation rate and, hence, increase the thickness of the resulting oxide at the trench edges. Embodiments include masking and etching a barrier nitride layer, forming protective spacers on portions of the substrate corresponding to subsequently formed trench edges, etching the trench, removing the protective spacers, ion implanting impurities into those portions of the substrate previously covered by the protective spacers, and then growing an oxide liner. The resulting oxide formed on the trench edges is thick due to the enhanced silicon oxidation rate, thereby avoiding overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.

Abstract: An insulated trench isolation structure is formed in a semiconductor substrate with an oxide or nitride spacer overlying and protecting a portion of a pad oxide layer at the trench edge such that the pad oxide layer acts as part of the gate oxide layer. Embodiments include providing a step between the trench fill and the pad oxide layer and forming the protective spacer thereon. The protective spacer protects the underlying portion of the pad oxide layer at the trench edge during pad oxide removal prior to forming a gate oxide. Therefore, it is only necessary to grow the gate oxide on the main surface of the substrate, not at the trench edges. The gate oxide can then be formed uniformly thin, while the remaining pad oxide at the trench edges is relatively thick.

Abstract: An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate using a simplified reverse source/drain planarization mask. Embodiments include forming trenches and refilling them with an insulating material which also covers a main surface of the substrate, polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches, furnace annealing to densify and strengthen the remaining insulating material, masking the insulating material above the large trenches, isotropically etching the insulating material, and polishing to planarize the insulating material. Since the insulating material is partially planarized and strengthened prior to etching, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches.

Abstract: A gate is formed on a semiconductor substrate by using a SiON film as both a bottom anti-reflective coating (BARC) and subsequently as a hardmask to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, and a SiON film over the conductive layer. The resist mask is formed on the SiON film. The SiON film improves the resist mask formation process and then serves as a hardmask during subsequent etching processes. Then the wafer stack is shaped to form one or more polysilicon gates by sequentially etching through selected portions of the SiON film and the gate conductive layer as defined by the etch windows in the original resist mask. Once the gate has been properly shaped, any remaining portions of either the resist mask or the SiON film are then removed.

Abstract: An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate using a simplified reverse source/drain planarization mask. Embodiments include forming trenches and refilling them with an insulating material which also covers the substrate surface, polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches, depositing a second, thin layer of insulating material filling seams in the insulating material above the small trenches, masking the insulating material above the large trenches, isotropically etching, and polishing to planarize the insulating material. Since the insulating material is partially planarized and the seams over the small trenches are filled, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches.

Abstract: An insulated trench isolation structure is formed in a semiconductor substrate omitting a barrier nitride polish stop layer while avoiding substrate damage, thereby simplifying trench formation and improving planarity. After trench fill, polishing is conducted to effect substantial planarization without exposing the substrate surface, thereby avoiding substrate damage. Etching is then conducted to expose the substrate surface. The omission of the barrier nitride polish stop avoids generation of a topographical step at the substrate/trench fill interface, thereby enhancing the accuracy of subsequent photolithographic techniques in forming features with minimal dimensions.

Abstract: A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges and protects the field oxide from gouging during post-gate processing, such as during the local interconnect etch, thereby allowing the formation of high-quality implanted junctions. Embodiments include forming a photoresist mask directly on a pad oxide layer which, in turn, is formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. After masking, the substrate is etched to form a trench, an oxide liner is grown in the trench surface, and a polish stop layer is deposited in the trench on the oxide liner and on the pad oxide layer. The polish stop layer is then masked to the trench edges, and the polish stop in the trench is anisotropically etched, to remove the polish stop at the bottom of the trenches leaving a portion overlying the side surfaces and edges of the trench on the oxide liner.

Abstract: Accurate photolighographic processing is achieved employing a stepper global alignment structure enabling formation thereon of a substantially transparent layer having a substantially planar upper surface. Embodiments include a set of global alignment marks comprising spaced apart trenches, each trench segmented into a plurality of narrow trenches spaced apart by uprights and forming a dummy topographical area of narrow trenches surrounding the set of alignment marks. The segmented trenches and the dummy topographical area effectively provide a substantially uniform topography enabling deposition of a transparent layer without steps and effective local planarization. Since the upper surface of the transparent layer is substantially planar, layers of material deposited on the transparent layer during subsequent processing also have a substantially planar upper surface, thereby enabling transmission of the signal produced by the alignment marks to the stepper with minimal distortion.

Abstract: An insulated trench isolation structure is formed in a semiconductor substrate omitting a barrier nitride polish stop layer, thereby simplifying the formation of the trench isolating structure, and enabling the substrate to be polished substantially flush with the trench fill. The planar trench fill-substrate interface avoids additional topography, thereby facilitating application of, and enhancing the accuracy of, photolithographic techniques in forming features with minimal dimensions.

Abstract: A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges. Embodiments include forming a photoresist mask directly on a pad oxide layer which, in turn, is formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. After masking, the substrate is etched to form a trench, an oxide liner is grown in the trench surface, and a polish stop layer is deposited over the oxide liner and the pad oxide layer. The polish stop layer is then masked to the trench edges, and the polish stop in the trench etched away. The trench is then filled with an insulating material, the insulating material is planarized, and the polish stop is removed by etching. Thus, the oxide liner is allowed to grow on the trench edges without the restraint of a polish stop, resulting in a thick, rounded oxide on the trench edges. Additionally, no polish stop layer remains in the trench to cause unwanted electrical effects.

Abstract: An insulated trench isolation structure is formed in a semiconductor substrate using a thin amorphous silicon or polysilicon polish stop layer by adding a reflectance compensation layer on the polish stop layer. As a result, the topological step between the main surface of the substrate and the uppermost surface of the trench fill is reduced, thereby facilitating the application and enhancing the accuracy of photolithographic techniques in forming features with minimal dimensions.

Abstract: The etch profile of side surfaces of a gate electrode is improved by heat treating the gate electrode layer after nitrogen implantation and before etching to form the gate electrode. Nitrogen implantation at high dosages to prevent subsequent impurity penetration through the gate dielectric layer, e.g., B penetration, amorphizes the upper portion of the gate electrode layer resulting in concave side surfaces upon etching to form the gate electrode. Heat treatment performed after nitrogen implantation can restore sufficient crystallinity so that, after etching the gate electrode layer, the side surfaces of the resulting gate electrode are substantially parallel.

Abstract: In an electric fence energizer there is an exterior earth connection such as an earth connection post (16). The electric fence energizer comprises in the conventional way a transformer (T) having a primary winding (L.sub.1) and a secondary winding (L.sub.2), one exterior terminal (9) of which is connected to the conductor (17) in the electric fence and the other exterior terminal (11) is connected to the earth connection, high voltage pulses being induced over the secondary winding (L.sub.2) when voltage pulses are applied over the primary winding (L.sub.1). For a determination of the quality of the earth connection, the voltage over a small part of the secondary winding (L.sub.2) is obtained capacitively by means of an extra winding (L.sub.3) in the transformer (T). For an evaluation of this voltage, it is connected, only for a determined polarity, to a charging circuit for a capacitor (C.sub.2), which is discharged over a known resistor (R.sub.2, R.sub.3). The voltage (V.sub.21) over this capacitor (C.sub.