Abstract: A system configured to perform low power mode wakeword detection is provided. A device reduces power consumption without compromising functionality by placing a primary processor into a low power mode and using a secondary processor to monitor for sound detection. The secondary processor stores input audio data in a buffer component while performing sound detection on the input audio data. If the secondary processor detects a sound, the secondary processor sends an interrupt signal to the primary processor, causing the primary processor to enter an active mode. While in the active mode, the primary processor performs wakeword detection using the buffered audio data. To reduce a latency, the primary processor processes the buffered audio data at an accelerated rate. In some examples, the device may further reduce power consumption by including a second buffer component and only processing the input audio data after detecting a sound.

Abstract: A multi-modal interactive apparatus provides for output and input using a plurality of modalities. A display presents image output and speakers provide audio output. A sensor module includes sensors such as a microphone array, camera, radar, ambient light sensor, and so forth. Based on how the apparatus is mounted to a supporting structure, in one implementation the overall orientation of the apparatus may be arranged to provide a desired field-of-view (FOV) to the sensors. For example, based on mounting height, the orientation places the sensor module on a top or bottom of the mounted device. Within the sensor module, one or more sensors may be mounted with a pitch angle that directs the FOV to encompass users during typical operation. In another implementation, the sensor module may be repositioned with respect to the apparatus to provide the desired FOV, such as moved from top to bottom.

Abstract: Conversion components may receive game video rendered in high-dynamic-range (HDR) and standard-dynamic-range (SDR) camera video of a game player. The conversion components may provide local video output to a local display and remote video output for network transmission to remote viewers. The SDR camera video may be converted to HDR and provided with HDR game video in the local video output. For HDR network transmission, the HDR game video and converted HDR camera video may be included in the remote video output. For SDR network transmission, the HDR game video may be converted to SDR and provided with the SDR camera video in the remote video output. The game video, camera video and other video feeds may have respective portals in the local and remote video outputs. The local and remote video outputs may have respective visual portal arrangements that may be at least partially different from one another.

Abstract: Conversion components may receive game video rendered in high-dynamic-range (HDR) and standard-dynamic-range (SDR) camera video of a game player. The conversion components may provide local video output to a local display and remote video output for network transmission to remote viewers. The SDR camera video may be converted to HDR and provided with HDR game video in the local video output. For HDR network transmission, the HDR game video and converted HDR camera video may be included in the remote video output. For SDR network transmission, the HDR game video may be converted to SDR and provided with the SDR camera video in the remote video output. The game video, camera video and other video feeds may have respective portals in the local and remote video outputs. The local and remote video outputs may have respective visual portal arrangements that may be at least partially different from one another.

Abstract: Conversion components may receive game video rendered in high-dynamic-range (HDR) and standard-dynamic-range (SDR) camera video of a game player. The conversion components may provide local video output to a local display and remote video output for network transmission to remote viewers. The SDR camera video may be converted to HDR and provided with HDR game video in the local video output. For HDR network transmission, the HDR game video and converted HDR camera video may be included in the remote video output. For SDR network transmission, the HDR game video may be converted to SDR and provided with the SDR camera video in the remote video output. The game video, camera video and other video feeds may have respective portals in the local and remote video outputs. The local and remote video outputs may have respective visual portal arrangements that may be at least partially different from one another.

Abstract: A system configured to enable a Wi-Fi processor to enter a low power mode (LPM) for short periods of time without compromising functionality is provided. A device reduces power consumption by enabling the Wi-Fi processor to enter LPM with scheduled wakeup events to enable specific functionality. In some examples, the Wi-Fi processor toggles between LPM and an active mode based on a first duty cycle to enable new device provisioning. The first duty cycle corresponds to a time required to scan a plurality of wireless channels, waking the Wi-Fi processor at a first frequency to monitor for incoming probe requests. In other examples, the Wi-Fi processor uses a second duty cycle chosen to maintain time synchronicity between a time master device and time follower devices. The device sets the second duty cycle to wake the Wi-Fi processor at a second frequency to exchange data packets with synchronized devices.

Abstract: A device has a camera that is moveable by one or more actuators. During operation the camera moves. For example, the camera may move to follow a user as they move within the physical space. Mechanical limitations result in the camera movement exhibiting discontinuities, such as small jerks or steps from one orientation to another while panning. If the camera is acquiring video data while moving, the resulting video data may appear jittery and be unpleasant for a user to view. An offset is determined between an intended orientation of the camera at a specified time and an actual orientation of the camera at that time. A portion of raw image data acquired at the specified time is cropped using the offset to produce cropped image data that is free from jitter due to the movement discontinuities.

Abstract: Techniques for processing video data are described. In an example, a device receives input video data having a first resolution. A first processor of the device sends, based at least in part on the input video data, first video data having the first resolution to a display. The device generates second video data from the input video data by at least down scaling the input video data to a second resolution, the second resolution being lower than the first resolution. A second processor of the device determines, while the first video data is presented, a property of the input video data based at least in part on the second video data. The second processor generates an indication of the property, where the indication is output while the first video data is presented.

Abstract: A system configured to enable a Wi-Fi processor to enter a low power mode (LPM) for short periods of time without compromising functionality is provided. A device reduces power consumption by enabling the Wi-Fi processor to enter LPM with scheduled wakeup events to enable specific functionality. In some examples, the Wi-Fi processor toggles between LPM and an active mode based on a first duty cycle to enable new device provisioning. The first duty cycle corresponds to a time required to scan a plurality of wireless channels, waking the Wi-Fi processor at a first frequency to monitor for incoming probe requests. In other examples, the Wi-Fi processor uses a second duty cycle chosen to maintain time synchronicity between a time master device and time follower devices. The device sets the second duty cycle to wake the Wi-Fi processor at a second frequency to exchange data packets with synchronized devices.

Abstract: A system configured to perform low power mode wakeword detection is provided. A device reduces power consumption without compromising functionality by placing a primary processor into a low power mode and using a secondary processor to monitor for sound detection. The secondary processor stores input audio data in a buffer component while performing sound detection on the input audio data. If the secondary processor detects a sound, the secondary processor sends an interrupt signal to the primary processor, causing the primary processor to enter an active mode. While in the active mode, the primary processor performs wakeword detection using the buffered audio data. To reduce a latency, the primary processor processes the buffered audio data at an accelerated rate. In some examples, the device may further reduce power consumption by including a second buffer component and only processing the input audio data after detecting a sound.

Abstract: The present invention relates to an image enhancement unit and a method of enhancing a first structure (S1) of samples into a second structure (S2) of samples, the first and the second structure both representing a first property of a scene and having a first resolution, based on a third structure (S3) of samples representing a second property and having the first resolution, the first property and the second property respectively representing different properties of substantially the same scene. The method comprising generating a fourth structure (S4) of samples representing the first property, the fourth structure (S4) of samples having a second resolution lower than the first resolution, by down-scaling first samples of the first structure (S1) of samples to form the samples of the fourth structure (S4) of samples.

Abstract: A system and method to render 3D images from a 2D source are described. An embodiment of a method to render 3D images from a 2D source comprises the steps of providing a graphics rendering device to estimate depth of a 2D image; providing video or graphics textures and depth-maps to describe an object in a 3D scene; creating, in one embodiment, a single view angle and in another preferred embodiment at least two view angles of the 3D scene to represent an intraocular distance using the graphics rendering device; and presenting both of the at least two view angles on a display using the graphics rendering device and especially the commonly available 3D imaging technology of the graphics rendering device.

Abstract: A processing element (1) forming part of a parallel processing array such as SIMD comprises an arithmetic logic unit (ALU) (3), a multiplexer (MUX) (5), an accumulator (ACCU) (7) and a flag register (FLAG) (9). The ALU is configured to operate on a common instruction received by all processing elements in the processing array. The processing element (1) further comprises a storage element (SE) (11), which supports the processing of local customized (i.e. data dependent) processing in the processing element (1), such as lookup table operations and the storing local coefficient data.

Abstract: Video stream processing, such as processing that includes MPEG decoding an subsequent post-processing involves using signal processing circuitry (102, 106) to execute a first and a second video stream processing function. The first video stream processing function produces frame data of successive video frames in a temporally ordered output sequence of frames. The second video stream processing function uses the frame data in an ordered input sequence of frames that differs from the output sequence, for example because later P-frames are needed to decode B frames. The frame data is buffered between application of the first and second video processing function to the frame data. A first and a second. buffer memory (12, 106) are used. The first buffer memory (12) is coupled to the signal processing circuitry via a shareable channel (15) such as an external IC terminals, but the processing circuitry does not use the shareable channel (15) to access the second buffer memory (106).

Abstract: A SIMD processor architecture comprises a Linear Processor Array (LPA) (41) having a plurality of Processing Elements (PEs) (42). Each PE (42) operates on its pixel data based on a common instruction which is broadcast to all PEs (42) from a global control processor (44). To enhance the processor's capability in handling de-interlacing algorithms, there is provided a field access module (FAM) (47), an input line memory (48), and a shadow memory (49) within a working line memory (43). The input line memory (48) comprises a previous video field memory (481) for storing a first plurality of pixels from a previous video field, a current video field memory (482) for storing a plurality of pixels from a current video field and a next video field memory (483) for storing a plurality of pixels from a next video field. In a similar manner, the shadow memory (49) comprises a previous-copy video field memory (491), a current-copy video field memory (492), and a next-copy video field memory (493).

Abstract: Aspects involve effectively separating communication hardware in a data processing system by introducing a communication device for each processor. By introducing this separation the processors can concentrate on performing their function-specific tasks, while the communication device provide the communication support for the respective processor. Accordingly, in certain embodiments, a data processing system is provided with a computation, a communication support and a communication network layer.

Abstract: The present invention relates to an image enhancement unit and a method of enhancing a first structure (S1) of samples into a second structure (S2) of samples, the first and the second structure both representing a first property of a scene and having a first resolution, based on a third structure (S3) of samples representing a second property and having the first resolution, the first property and the second property respectively representing different properties of substantially the same scene. The method comprising generating a fourth structure (S4) of samples representing the first property, the fourth structure (S4) of samples having a second resolution lower than the first resolution, by down-scaling first samples of the first structure (S1) of samples to form the samples of the fourth structure (S4) of samples.

Abstract: A processing circuit executes a data producing process and a data consuming process. The data producing process produces a stream of data, the data consuming process consumes the stream of data concurrently with production of the stream. A first-in first-out buffer passes data from the stream between the data producing process and the data consuming process. The buffer comprises buffer memory, the buffer writes data-items from the stream in circular fashion into the buffer memory. A consuming process interface is arranged to process a command for making a data grain from the stream available to the data consuming process. The interface responds to the command by testing whether addresses of data within the grain to which access has to be gained wrap around in the circular FIFO buffer.

Abstract: An electronic device is provided comprising a plurality of processing units (IP; MIP, SIP); an interconnect means (NOC) for coupling the plurality of processing units (IP; MIP, SIP); and a plurality of interia.ee means (NI; MNI, SNI) arranged between one of the processing units (IP; MIP, SIP) and the interconnect means (NOC), for enabling a communication between the processing units (IP; MIP, SIP) and the interconnect means. The communication between the processing units (IP; MIP, SIP) is a packet-based communication via the interface means (NI; MNI, SNI) and the interconnect means (NOC). Each packet first comprises a first header (H) followed by a pay load (P).

Abstract: An integrated circuit comprising a plurality of processing modules (M, S; IP) and a network (N) arranged for coupling said modules (M, S; IP) is provided. Said integrated circuit further comprises a plurality of network interfaces (NI) each being coupled between one of said processing modules (M, S; IP) and said network (N). Said network (N) comprises a plurality of routers (R) coupled via network links (L) to adjacent routers (R). Said processing modules (M, S; IP) communicate between each other over connections using connection paths (C1-C12) through the network (N), wherein each of said connection paths (C1-C12) employ at least one network link (L) for a required number of time slots. At least one time slot allocating unit (SA) is provided for allocating time slots to said network links (L) for determining unused time slots and for allocation the determined unused time slots to one or more of the connections using said network link in addition to its already allocated time slots.