Patents by Inventor Omer Katz

Omer Katz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11972149
    Abstract: A storage system is provided that performs a defragmentation operation or proactive garbage collection in its memory based on a command from a host. The command specifies which blocks in the memory should take part in the defragmentation operation by specifying a maximum amount of valid data that a block can have to qualify for defragmentation. That way, the storage system only performs defragmentation on those blocks that meet the validity criteria provided by the host. This can help improve performance of the storage system while reducing the degree of negative tradeoffs that may come with defragmentation or proactive garbage collection.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: April 30, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Nadav Sober, Omer Katz
  • Publication number: 20240036764
    Abstract: A storage system is provided that performs a defragmentation operation or proactive garbage collection in its memory based on a command from a host. The command specifies which blocks in the memory should take part in the defragmentation operation by specifying a maximum amount of valid data that a block can have to qualify for defragmentation. That way, the storage system only performs defragmentation on those blocks that meet the validity criteria provided by the host. This can help improve performance of the storage system while reducing the degree of negative tradeoffs that may come with defragmentation or proactive garbage collection.
    Type: Application
    Filed: July 27, 2022
    Publication date: February 1, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Nadav Sober, Omer Katz
  • Publication number: 20230268363
    Abstract: A method for manufacturing optical unit, the method includes (a) obtaining an intermediate optical unit that comprises a semiconductor portion, a transparent organic layer, the array of organic microlenses and a protective layer; (b) depositing a protective mask above a first protective layer region; (c) removing, by applying a first etch process, the second protective layer region to expose a second region of the transparent organic layer; and (d) removing, by applying a second etch process, the second region of the transparent organic layer to expose the contact pads and removing the protective mask while maintaining the first protective layer portion.
    Type: Application
    Filed: February 22, 2022
    Publication date: August 24, 2023
    Applicant: Tower Semiconductor Ltd.
    Inventors: Naor INBAR, Omer KATZ, Tzur MILLER, Ayala ELKAYAM
  • Patent number: 9231020
    Abstract: Some demonstrative embodiments include devices and/or methods of gettering on silicon on insulator (SOI) substrate. For example, a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) may include a plurality of pixels arranged on a wafer, a pixel of the pixels including: a silicon active area; at least one non-silicided leakage-sensitive component formed on the active area, the leakage-sensitive component is sensitive to metal contaminants; a non-leakage-sensitive area formed on the active area, the non-leakage-sensitive area surrounding the leakage-sensitive component; and at least one silicided gettering region formed on the non-leakage-sensitive area to trap the metal contaminants.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: January 5, 2016
    Assignee: TOWER SEMICONDUCTOR LTD.
    Inventors: Dmitry Veinger, Assaf Lahav, Omer Katz, Ruthie Shima-Edelstein
  • Publication number: 20150200227
    Abstract: Some demonstrative embodiments include devices and/or methods of gettering on silicon on insulator (SOI) substrate. For example, a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) may include a plurality of pixels arranged on a wafer, a pixel of the pixels including: a silicon active area; at least one non-silicided leakage-sensitive component formed on the active area, the leakage-sensitive component is sensitive to metal contaminants; a non-leakage-sensitive area formed on the active area, the non-leakage-sensitive area surrounding the leakage-sensitive component; and at least one silicided gettering region formed on the non-leakage-sensitive area to trap the metal contaminants.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 16, 2015
    Inventors: Dmitry Veinger, Assaf Lahav, Omer Katz, Ruthie Shima-Edelstein