Abstract: A synchronous semiconductor memory device satisfying the CAS function requirement of JEDEC is provided. Through command input pins and address input pins, external command signals and address signals are applied. A command decoder decodes the applied command signals. A write command latency control unit, a read command latency control unit, and a column address latency control unit delay a write command, a read command, and a column address signal, respectively, for a time period equal to N/2 times a clock signal cycle in response to a latency control signal. N is an integer equal to or greater than zero, and the latency control signal is activated in response to a value set in an extended mode register set.

Abstract: Disclosed is a column address decoder of a semiconductor memory device for decoding column addresses to enable a corresponding column select line, the column address decoder comprising a column address pre-decoder for latching combinations of the column addresses when a column select line enable signal is in a first level, and outputting the latched result as pre-decoded column addresses when the column select line enable signal is in a second level and a column address main decoder for combining the pre-decoded column addresses and enabling the corresponding column select line among a plurality of column address select lines.

Abstract: Integrated circuit memory devices that utilize preferred masking techniques include a memory cell array and a mask signal generator that generates first and second internal data masking signals in response to at least one single data rate mode signal. A data controller is also provided to pass input write data to the memory cell array when the first and second internal data masking signals are inactive and mask at least a portion of the input write data from the memory cell array when one of the first and second internal data masking signals is active. This ability to mask data facilitates operation of the memory device in a specialized single data rate mode for testing using conventional test equipment.

Abstract: Integrated circuit memory devices that utilize preferred masking techniques include a memory cell array and a mask signal generator that generates first and second internal data masking signals in response to at least one single data rate mode signal. A data controller is also provided to pass input write data to the memory cell array when the first and second internal data masking signals are inactive and mask at least a portion of the input write data from the memory cell array when one of the first and second internal data masking signals is active. This ability to mask data facilitates operation of the memory device in a specialized single data rate mode for testing using conventional test equipment.