Patents by Inventor Ono Takashi
Ono Takashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10164276Abstract: A fuel cell device is improved for operating conditions during a partial load operation. The fuel cell device comprises a cell stack formed by electrically connecting fuel cells for generating power by fuel gas and oxygen-containing gas; a fuel gas supply unit for supplying the fuel gas to the fuel cells; and a power adjustment unit for adjusting the amount of current that is supplied to an external load and a controller for controlling the fuel gas supply unit and the power adjustment unit. The controller adjusts, during the partial load operation of the fuel cell device and when the fuel gas supplied to the cell stack is at low flow rate. The a relationship between a fuel utilization rate of the cell stack and the amount of power generated by the cell stack can be nonlinear.Type: GrantFiled: July 29, 2010Date of Patent: December 25, 2018Assignee: KYOCERA CORPORATIONInventors: Ono Takashi, Mitsuhiro Nakamura, Naruto Takahashi
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Publication number: 20120183876Abstract: A fuel cell device and a method of operating the same, the fuel cell device being provided with a container; a cell stack stored inside the container, the cell stack comprising a plurality of fuel cells operable to generate electric power; a gas supply unit to supply oxygen-containing gas to the fuel cells; a supplying-power conditioning unit operable to adjust the quantity of generated electric power in the cell stack; a thermal sensor outside the container, operable to measure a measured temperature of the oxygen-containing gas supplied to the fuel cells; and a control unit operable to control the gas supply unit and the power conditioning unit such an amount of oxygen-containing gas supplied from the gas supply unit is increased if the measured temperature is higher than a predetermined temperature.Type: ApplicationFiled: September 28, 2010Publication date: July 19, 2012Inventors: Ono Takashi, Mitsuhiro Nakamura, Naruto Takahashi
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Publication number: 20120148933Abstract: A fuel cell device is improved for operating conditions during a partial load operation. The fuel cell device comprises a cell stack formed by electrically connecting fuel cells for generating power by fuel gas and oxygen-containing gas; a fuel gas supply unit for supplying the fuel gas to the fuel cells; and a power adjustment unit for adjusting the amount of current that is supplied to an external load and a controller for controlling the fuel gas supply unit and the power adjustment unit. The controller adjusts, during the partial load operation of the fuel cell device and when the fuel gas supplied to the cell stack is at low flow rate. The a relationship between a fuel utilization rate of the cell stack and the amount of power generated by the cell stack can be nonlinear.Type: ApplicationFiled: July 29, 2010Publication date: June 14, 2012Applicant: KYOCERA CORPORATIONInventors: Ono Takashi, Mitsuhiro Nakamura, Naruto Takahashi
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Patent number: 6693346Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: January 14, 2003Date of Patent: February 17, 2004Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics Co., Ltd.Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Publication number: 20030098504Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: ApplicationFiled: January 14, 2003Publication date: May 29, 2003Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Patent number: 6521993Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: April 18, 2002Date of Patent: February 18, 2003Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor Ltd., Akita Electronics Co., Ltd.Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Publication number: 20020121690Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: ApplicationFiled: April 18, 2002Publication date: September 5, 2002Applicant: Hitachi, Ltd. (JP)Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Patent number: 6424030Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: May 24, 2001Date of Patent: July 23, 2002Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics Co., Ltd.Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Publication number: 20010020741Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: ApplicationFiled: May 24, 2001Publication date: September 13, 2001Applicant: Hitachi Ltd.Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Patent number: 6262488Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: April 16, 1999Date of Patent: July 17, 2001Assignees: Hitachi Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics, Co., Ltd.,Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Patent number: 5708298Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: December 10, 1996Date of Patent: January 13, 1998Assignees: Hitachi Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics, Co., Ltd.Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Patent number: 5587341Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: October 18, 1994Date of Patent: December 24, 1996Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics Co., Ltd.Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Patent number: 5138438Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: November 25, 1991Date of Patent: August 11, 1992Assignees: Akita Electronics Co. Ltd., Hitachi Ltd., Hitachi Semiconductor Ltd.Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Patent number: 4406388Abstract: Method for conveying strip materials in a floated manner whereby a strip is allowed to pass between a pair of chambers vertically spaced apart from each other and provided with a plurality of jets or blow-off openings at one surface thereof so that jets of gases are blown therefrom against the strip so as to float the strip. If the strip to be conveyed is of a smaller width, then the width of gases blown from the lower chamber are correspondingly reduced so that a saving of energy required for blowing the gases may be achieved.Type: GrantFiled: March 19, 1982Date of Patent: September 27, 1983Assignee: Daido Tokushuko Kabushiki KaishaInventors: Ono Takashi, Suda Tsuyoshi