Patents by Inventor Ono Takashi

Ono Takashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10164276
    Abstract: A fuel cell device is improved for operating conditions during a partial load operation. The fuel cell device comprises a cell stack formed by electrically connecting fuel cells for generating power by fuel gas and oxygen-containing gas; a fuel gas supply unit for supplying the fuel gas to the fuel cells; and a power adjustment unit for adjusting the amount of current that is supplied to an external load and a controller for controlling the fuel gas supply unit and the power adjustment unit. The controller adjusts, during the partial load operation of the fuel cell device and when the fuel gas supplied to the cell stack is at low flow rate. The a relationship between a fuel utilization rate of the cell stack and the amount of power generated by the cell stack can be nonlinear.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: December 25, 2018
    Assignee: KYOCERA CORPORATION
    Inventors: Ono Takashi, Mitsuhiro Nakamura, Naruto Takahashi
  • Publication number: 20120183876
    Abstract: A fuel cell device and a method of operating the same, the fuel cell device being provided with a container; a cell stack stored inside the container, the cell stack comprising a plurality of fuel cells operable to generate electric power; a gas supply unit to supply oxygen-containing gas to the fuel cells; a supplying-power conditioning unit operable to adjust the quantity of generated electric power in the cell stack; a thermal sensor outside the container, operable to measure a measured temperature of the oxygen-containing gas supplied to the fuel cells; and a control unit operable to control the gas supply unit and the power conditioning unit such an amount of oxygen-containing gas supplied from the gas supply unit is increased if the measured temperature is higher than a predetermined temperature.
    Type: Application
    Filed: September 28, 2010
    Publication date: July 19, 2012
    Inventors: Ono Takashi, Mitsuhiro Nakamura, Naruto Takahashi
  • Publication number: 20120148933
    Abstract: A fuel cell device is improved for operating conditions during a partial load operation. The fuel cell device comprises a cell stack formed by electrically connecting fuel cells for generating power by fuel gas and oxygen-containing gas; a fuel gas supply unit for supplying the fuel gas to the fuel cells; and a power adjustment unit for adjusting the amount of current that is supplied to an external load and a controller for controlling the fuel gas supply unit and the power adjustment unit. The controller adjusts, during the partial load operation of the fuel cell device and when the fuel gas supplied to the cell stack is at low flow rate. The a relationship between a fuel utilization rate of the cell stack and the amount of power generated by the cell stack can be nonlinear.
    Type: Application
    Filed: July 29, 2010
    Publication date: June 14, 2012
    Applicant: KYOCERA CORPORATION
    Inventors: Ono Takashi, Mitsuhiro Nakamura, Naruto Takahashi
  • Patent number: 6693346
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: February 17, 2004
    Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics Co., Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Publication number: 20030098504
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Application
    Filed: January 14, 2003
    Publication date: May 29, 2003
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Patent number: 6521993
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: February 18, 2003
    Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor Ltd., Akita Electronics Co., Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Publication number: 20020121690
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Application
    Filed: April 18, 2002
    Publication date: September 5, 2002
    Applicant: Hitachi, Ltd. (JP)
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Patent number: 6424030
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: July 23, 2002
    Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics Co., Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Publication number: 20010020741
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Application
    Filed: May 24, 2001
    Publication date: September 13, 2001
    Applicant: Hitachi Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Patent number: 6262488
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: April 16, 1999
    Date of Patent: July 17, 2001
    Assignees: Hitachi Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics, Co., Ltd.,
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Patent number: 5708298
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: January 13, 1998
    Assignees: Hitachi Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics, Co., Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Patent number: 5587341
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: October 18, 1994
    Date of Patent: December 24, 1996
    Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics Co., Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Patent number: 5138438
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: November 25, 1991
    Date of Patent: August 11, 1992
    Assignees: Akita Electronics Co. Ltd., Hitachi Ltd., Hitachi Semiconductor Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Patent number: 4406388
    Abstract: Method for conveying strip materials in a floated manner whereby a strip is allowed to pass between a pair of chambers vertically spaced apart from each other and provided with a plurality of jets or blow-off openings at one surface thereof so that jets of gases are blown therefrom against the strip so as to float the strip. If the strip to be conveyed is of a smaller width, then the width of gases blown from the lower chamber are correspondingly reduced so that a saving of energy required for blowing the gases may be achieved.
    Type: Grant
    Filed: March 19, 1982
    Date of Patent: September 27, 1983
    Assignee: Daido Tokushuko Kabushiki Kaisha
    Inventors: Ono Takashi, Suda Tsuyoshi