Patents by Inventor Ophir Turbovich

Ophir Turbovich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11748539
    Abstract: A method and a system for converting a variable delay in real number modeling code to cycle-driven simulation interface event for digital/mixed signal emulation is provided. The method comprises identifying a variable delay of an analog signal in real number modeling code defining an analog circuit; determining a frequency and a maximum number of cycles for a series of discrete clock cycles, wherein the variable delay corresponds to one cycle in the series of discrete clock cycles; converting the variable delay into a plurality of cycle-driven discrete events based on the series of discrete clock cycles; and generating synthesizable code based on the plurality of cycle-driven discrete events for digital mixed signal emulation. A system and a non-transitory computer readable medium to perform the above method are also provided.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 5, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ophir Turbovich, Yosinori Watanabe
  • Patent number: 11216606
    Abstract: A computer implemented method for functional safety verification includes simulating SA0 and/or SA1 faults at a Q output port of each sequential element in a first representation of an electronic design, to determine whether any of the simulated faults is detectable by a safety mechanism, determining, based on one or more fault relation rules and based on a second gate-level representation of the electronic design, whether any of the faults is also detectable by the safety mechanism if occurred at one or more input ports of the respective sequential element or one or more input ports of a clockgate of the respective sequential element, and identifying a remainder of input ports and input ports of a clockgate of each of the sequential elements at which the faults are not determined to be detectable by the safety mechanism based on the one or a plurality of fault relation rules.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: January 4, 2022
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ophir Turbovich, Muhammad Zoabi, Yuval Shpak
  • Patent number: 10262088
    Abstract: A method for converting real number modeling to cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, cleaning the real number modeling code in the file, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in the circuit design, and selecting a real number modeling file from the circuit design. For the real number modeling file, the method includes parsing the real number modeling file, building a header file associated with the real number modeling file, and building a compilation file associated with the cycle-driven simulation interface file. A system and a non-transitory, computer readable medium to perform the above method are also provided.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: April 16, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ophir Turbovich, Yosinori Watanabe
  • Patent number: 10262095
    Abstract: A method for converting real number modeling to a cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, requesting a user input parameter, converting the file to a cycle-driven simulation interface file based on the user input parameter, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in the circuit design, and selecting a real number modeling file from the circuit design. For the real number modeling file, the method includes parsing the real number modeling file, building a header file associated with the real number modeling file, and building a compilation file associated with the cycle-driven simulation interface file. A system and a computer readable medium to perform the above method are also provided.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 16, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ophir Turbovich, Yosinori Watanabe
  • Patent number: 10133836
    Abstract: A method for on-the-fly determination of leakage power and temperature of an electronic circuit design is provided. The method includes calculating a dynamic power of the electronic circuit design. The method also includes calculating a total power consumption of the electronic circuit design. The method further includes averaging the total power consumption to obtain an average total power, determining a temperature of the electronic circuit design based on the average total power, and determining a leakage power of the electronic circuit design based on the temperature. A system and a non-transitory, computer-readable medium storing computer-readable instructions to perform the above method are also provided.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: November 20, 2018
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ophir Turbovich, Vasant Ramabadran
  • Patent number: 10133837
    Abstract: A method for converting a real number modeling to a synthesizable register-transfer level emulation in digital mixed signal environments is provided. The method includes verifying an input in a file including a real number modeling code and cleaning the real number modeling code in the file. The method also includes separating a clean register-transfer level code from the real number modeling code, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. The method further includes converting the cycle-driven simulation interface file into a register-transfer level file suitable to perform a circuit emulation in digital mixed signal environments, and verifying that the register-transfer level file is ready to perform circuit emulation in the digital mixed signal environments. A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: November 20, 2018
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ophir Turbovich, Yosinori Watanabe, Michael Young, Sean Dart
  • Patent number: 8732384
    Abstract: A device and methods are provided for accessing memory. In one embodiment, a method includes receiving a request for data stored in a device, checking a local memory for data based on the request to determine if one or more blocks of data associated with the request are stored in the local memory, and generating a memory access request for one or more blocks of data stored in a memory of the device based when one or more blocks of data are not stored in the local memory. In one embodiment, data stored in memory of the device may be arranged in a configuration to include a plurality of memory access units each having adjacent lines of pixel data to define a single line of memory within the memory access units. Memory access units may be configured based on memory type and may reduce the number of undesired pixels read.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: May 20, 2014
    Assignee: CSR Technology Inc.
    Inventors: Eran Scharam, Costia Parfenyev, Liron Ain-Kedem, Ophir Turbovich, Tuval Berler
  • Patent number: 8375145
    Abstract: A network interface adapter provides a host processor with two complementary modes of submitting descriptors to be executed by the adapter: a normal mode, in which the host writes descriptors to a system memory and rings an assigned doorbell to notify the adapter; and a priority mode, in which the host writes the descriptor itself to a doorbell address of the adapter. In the priority mode, the adapter is relieved of the need to read the descriptor from the memory, and can thus begin execution as soon as it has resources available to do so.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: February 12, 2013
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Michael Kagan, Diego Crupnicoff, Ophir Turbovich, Margarita Shnitman, Ariel Shachar, Gil Bloch
  • Patent number: 7653754
    Abstract: A method for preventing deadlock in communication between a host software application and a network interface card (NIC), comprises writing a doorbell associated with at least one descriptor having a descriptor context to a buffer in the NIC, dropping at least one doorbell from the buffer if the buffer is full, thereby allowing a write of a new doorbell to the buffer, and recovering each dropped doorbell for further execution of descriptors associated with this doorbell. The descriptor execution is in order of posting by the application to the NIC. A system implementing the method comprises a doorbell drop mechanism and a doorbell recovery mechanism.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: January 26, 2010
    Assignee: Mellanox Technologies Ltd.
    Inventors: Michael Kagan, Benny Koren, Dror Goldenberg, Gilad Shainer, Gil Bloch, Ariel Shachar, Ophir Turbovich, Dror Borer, Diego Crupnicoff
  • Publication number: 20050198410
    Abstract: A method for preventing deadlock in communication between a host software application and a network interface card (NIC), comprises writing a doorbell associated with at least one descriptor having a descriptor context to a buffer in the NIC, dropping at least one doorbell from the buffer if the buffer is full, thereby allowing a write of a new doorbell to the buffer, and recovering each dropped doorbell for further execution of descriptors associated with this doorbell. The descriptor execution is in order of posting by the application to the NIC. A system implementing the method comprises a doorbell drop mechanism and a doorbell recovery mechanism.
    Type: Application
    Filed: January 5, 2004
    Publication date: September 8, 2005
    Inventors: Michael Kagan, Benny Koren, Dror Goldenberg, Gilad Shainer, Gil Bloch, Ariel Shachar, Ophir Turbovich, Dror Borer, Diego Crupnicoff
  • Publication number: 20020165897
    Abstract: A network interface adapter provides a host processor with two complementary modes of submitting descriptors to be executed by the adapter: a normal mode, in which the host writes descriptors to a system memory and rings an assigned doorbell to notify the adapter; and a priority mode, in which the host writes the descriptor itself to a doorbell address of the adapter. In the priority mode, the adapter is relieved of the need to read the descriptor from the memory, and can thus begin execution as soon as it has resources available to do so.
    Type: Application
    Filed: January 23, 2002
    Publication date: November 7, 2002
    Inventors: Michael Kagan, Diego Crupnicoff, Ophir Turbovich, Margarita Shnitman, Ariel Shachar, Gil Bloch