Patents by Inventor Or Inbar

Or Inbar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11436133
    Abstract: Example implementations relate to comparable UI object identifications. Some implementations may include a data capture engine to capture data points during test executions of the application under test. The data points may include, for example, test action data and application action data. Additionally, some implementations may include a data correlation engine to correlate each of the data points with a particular test execution of the test executions, and each of the data points may be correlated based on a sequence of events that occurred during the particular test execution. Furthermore, some implementations may also automatically identify, based on the correlated data points, a set of comparable UI objects.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: September 6, 2022
    Assignee: Micro Focus LLC
    Inventors: Inbar Shani, Ilan Shufer, Amichai Nitsan
  • Patent number: 11435920
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: September 6, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Einav Zilberstein, Karin Inbar
  • Publication number: 20220268644
    Abstract: A semiconductor integrated circuit (IC) comprising: a first ring oscillator (ROSC) circuit and a second ROSC circuit at spaced apart locations in the IC, each ROSC circuit having a respective oscillation frequency in operation that varies with temperature; a semiconductor temperature sensor, located in the IC proximate to the first ROSC circuit and providing a sensor output signal indicative of temperature; and at least one processor, configured to indicate a temperature at the second ROSC circuit based at least on: the sensor output signal, the oscillation frequency of the second ROSC circuit, and the oscillation frequency of the first ROSC circuit.
    Type: Application
    Filed: July 29, 2020
    Publication date: August 25, 2022
    Inventors: Eyal FAYNEH, Guy REDLER, Evelyn LANDMAN, Inbar WEINTROB, Yahel DAVID, Faten TANASRA
  • Publication number: 20220260630
    Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.
    Type: Application
    Filed: March 24, 2022
    Publication date: August 18, 2022
    Inventors: Eyal FAYNEH, Edi SHMUELI, Alexander BURLAK, Evelyn LANDMAN, Inbar WEINTROB, Yahel DAVID, Shai COHEN, Guy REDLER
  • Patent number: 11408932
    Abstract: Determination of one or more operating conditions (leakage current, temperature and/or workload) of a functional transistor in a semiconductor integrated circuit (IC). The functional transistor provides an electrical current, which is provided as an input to a ring oscillator (ROSC). The ROSC is located in the IC proximate to the functional transistor and has an oscillation frequency in operation. The one or more operating conditions of the functional transistor are determined based on the oscillation frequency of the ROSC.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: August 9, 2022
    Assignee: PROTEANTECS LTD.
    Inventors: Eyal Fayneh, Inbar Weintrob, Evelyn Landman, Yahel David, Shai Cohen, Guy Redler
  • Publication number: 20220233681
    Abstract: Disclosed herein are transgenic Salmonella typhi Ty21a comprising a chromosome with one or more heterologous nucleic acid regions, wherein the heterologous nucleic acid regions encode one or more viral antigens and are integrated into the Salmonella typhi Ty21a chromosome, and wherein the transgenic Salmonella typhi Ty21a stably expresses the one or more viral antigens. Also disclosed herein are compositions and vaccines comprising the transgenic Salmonella typhi Ty21a. Also disclosed herein are methods of eliciting an immune response in a subject against a SARS-CoV-2 viral antigen and/or a Salmonella typhi antigen comprising administering one or more doses of the composition or the vaccine to the subject. Also disclosed herein are methods of treating, preventing or reducing the incidence of COVID-19 and/or typhoid fever in a subject comprising administering one or more doses of the composition or the vaccine to the subject.
    Type: Application
    Filed: December 31, 2021
    Publication date: July 28, 2022
    Inventors: Betty Kim Lee SIM, Tint Tint WAI, Ehud INBAR, Stephen L. HOFFMAN
  • Publication number: 20220229555
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.
    Type: Application
    Filed: February 24, 2021
    Publication date: July 21, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Einav Zilberstein, Karin Inbar
  • Patent number: 11391771
    Abstract: A semiconductor integrated circuit (IC) comprising a time-to-digital converter circuit (TDC), wherein time inputs to the TDC are (i) one or more input to an input/output (I/O) buffer of a pad of the IC, and (ii) one or more output from the I/O buffer. The IC comprises a digital comparator circuit electrically configured to: receive a stream of digital output values from the TDC, compare each value of the stream to one or more previous value in the stream, and when the comparison reflects a difference value greater than a threshold, issuing a notification to a user of the IC.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: July 19, 2022
    Assignee: PROTEANTECS LTD.
    Inventors: Eyal Fayneh, Shai Cohen, Evelyn Landman, Yahel David, Inbar Weintrob
  • Patent number: 11385282
    Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: July 12, 2022
    Assignee: PROTEANTECS LTD.
    Inventors: Evelyn Landman, Shai Cohen, Yahel David, Eyal Fayneh, Inbar Weintrob
  • Publication number: 20220199156
    Abstract: The present disclosure generally relates to data storage devices, such as solid state drives (SSDs). A read threshold calibration operation is utilized to generate a calibrated read threshold for one or more voltage states of a cell of a MLC memory. A single-level cell (SLC) read is then executed to sense the ratio of bit values at the read thresholds of the voltage states, where SLC read refers to reading at a single read threshold, rather than to the cell type. The sensing results in a binary page with certain statistics of 1's and 0's. The ratio of 1's (or 0's) in the binary page is used to determine a deviation from the expected ratio, where the deviation is used to adjust the calibrated read threshold to match the voltage states of the MLC memory.
    Type: Application
    Filed: February 24, 2021
    Publication date: June 23, 2022
    Inventors: Eran SHARON, Karin INBAR, Alexander BAZARSKY, Dudy David AVRAHAM, Rohit SEHGAL, Gilad KOREN
  • Patent number: 11365174
    Abstract: An effective therapeutic agent for the M2 channel comprising sulfonylamide or oxabicyclo structures effective for treating amantadine-resistant influenza A infections, and methods of treating amantadine-resistant influenza A infections through administration of the same.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: June 21, 2022
    Assignees: Thomas Jefferson University, Ramot At Tel-Aviv University LTD.
    Inventors: Nir Ben-Tal, Roger S. Armen, Laurence C. Eisenlohr, Jitendra Belani, Michael Miller, Inbar Fish, Ori Kalid
  • Publication number: 20220189500
    Abstract: A system capable of speech gap modulation is configured to: receive at least one composite speech portion, which comprises at least one speech portion and at least one dynamic-gap portion, wherein the speech portion(s) comprising at least one variable-value speech portion, wherein the dynamic-gap portion(s) associated with a pause in speech; receive at least one synchronization point, wherein synchronization point(s) is associating a point in time in the composite speech portion(s) and a point in time in other media portion(s); and modulate dynamic-gap portion(s), based at least partially on the at variable-value speech portion(s), and on the point(s), thereby generating at least one modulated composite speech portion. This facilitates improved synchronization of the modulated composite speech portion(s) and the other media portion(s) at the synchronization point(s), when combining the other media portion(s) and the audio-format modulated composite speech portion(s) into a synchronized multimedia output.
    Type: Application
    Filed: January 30, 2020
    Publication date: June 16, 2022
    Inventors: Zohar SHERMAN, Ori INBAR
  • Patent number: 11357959
    Abstract: Various systems and methods are provided for reducing pressure at an outflow of a duct, such as the thoracic duct or the lymphatic duct, for example, the right lymphatic duct. A catheter system can be configured to be at least partially implanted within a vein of a patient in the vicinity of an outflow port of a duct of the lymphatic system. The catheter system includes first and second selectively deployable restriction members each configured to be activated to at least partially occlude the vein within which the catheter is implanted and to thus restrict fluid within a portion of the vein. The catheter system includes an impeller configured to be driven by a motor to induce a low pressure zone between the restriction members by causing blood to be pumped through the catheter when the restriction members occlude the vein.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: June 14, 2022
    Assignee: White Swell Medical Ltd
    Inventors: Yaacov Nitzan, Sagi Raz, Shani Chen, Or Inbar
  • Publication number: 20220182482
    Abstract: Systems and methods are provided for selectively restricting a mobile device. In one implementation, a visual capture can be to identify one or more indicators within the visual capture. Based on the indicators, an implementation of a restriction at the mobile device can be adjusted. In another implementation inputs can be processed to compute a determination, determination reflecting at least one of the in-vehicle role of the user as a driver and the in-vehicle role of the user as a passenger; and, an operation state of the mobile device can be modified based on such a determination. According to another implementation, one or more outputs can be projected from a mobile device, inputs can be received, and such inputs and outputs can be processed to determine a correlation between them. A restriction can then be modified based on the correlation.
    Type: Application
    Filed: July 19, 2021
    Publication date: June 9, 2022
    Inventors: Dan Abramson, Itzhak Pomerantz, Yuval Kashtan, Sean Ir, Ohad Inbar, Talia Lavie, Shay Gigi
  • Publication number: 20220164140
    Abstract: A data storage device including a non-volatile memory device including one or more non-volatile memory sets and one or more endurance groups. Each of the endurance groups includes at least one of the non-volatile memory sets. The data storage device includes a controller coupled to the non-volatile memory device. The controller is configured to receive a pending command message from a host interface, where the received pending command message includes a command configured to be executed by a first endurance group of the number of endurance groups. The controller is further configured to determine an assigned command slot for storing the command, where the assigned command slot is selected form one of a private command slot pool associated with the first endurance group or a shared command slot pool, fetch the command from the host device, and store the fetched command in the assigned command slot.
    Type: Application
    Filed: February 17, 2021
    Publication date: May 26, 2022
    Inventors: Shay Benisty, Karin Inbar
  • Patent number: 11340810
    Abstract: Methods and apparatus for managing and optimizing data storage devices that include non-volatile memory (NVM) are described. One such method involves deriving a hint for one or more logical block addresses (LBAs) of a storage device based on information received from a host device and/or physical characteristics of the storage device, such as LBAs that are invalidated together; grouping the LBAs into one or more clusters of LBAs based on the derived hint and a statistical analysis of the physical characteristics of the storage devices; allocating available physical block addresses (PBAs) in the storage device to one of the LBAs based on the one or more clusters of LBAs to achieve optimization of a data storage device.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 24, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ariel Navon, Alexander Bazarsky, Judah Gamliel Hahn, Karin Inbar, Rami Rom, Idan Alrod, Eran Sharon
  • Publication number: 20220156000
    Abstract: The present disclosure generally relates to efficient data transfer management of zone-append commands for a zoned namespace (ZNS). The ZNS storage device comprises a memory device having a plurality of memory dies, and a controller coupled to the memory device The controller receives a plurality of zone append commands, each zone append command being associated with a zone identification identifying a zone of a plurality of zones, and fetches and aggregates data associated with each zone append command by the zone identification in an append write buffer. The aggregated data is written to the memory device upon the aggregated data for each zone reaching a predetermined programming chunk size, or to a temporary buffer if the predetermined write size is not met. Each zone uses a separate channel when sending the aggregated data for programming to the memory device, allowing multiple channels to be utilized in parallel.
    Type: Application
    Filed: February 24, 2021
    Publication date: May 19, 2022
    Inventors: Karin INBAR, Shay BENISTY
  • Publication number: 20220156206
    Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Inventors: Eyal FAYNEH, Evelyn LANDMAN, Shai COHEN, Guy REDLER, Inbar WEINTROB
  • Patent number: 11327523
    Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Eyal Fayneh, Elias Nassar, Inbar Falkov, Ramkumar Krithivasan, Vijay K. Vuppaladadium, Miguel A. Corvacho Hernandez, Samer Nassar, Yair Talker
  • Publication number: 20220121627
    Abstract: Mechanisms, including systems, methods, and non-transitory computer readable media, for implementing conflict-free replicated data types in in-memory data structures are provided, the mechanisms comprising: a memory; and at least one hardware processor coupled to the memory and collectively configured to: mark a first key of a conflict-free replicated data type as to be deleted; send an update message reflecting that the first key is to be deleted to a first replica of an in-memory data structure; receive a plurality of messages each acknowledging that the first key is to be deleted; determine that the plurality of messages includes a message for each of a plurality of shards of the first replica; and in response to determining that the plurality of messages includes a message for each of the plurality of shards of the first replica, delete the first key.
    Type: Application
    Filed: October 20, 2021
    Publication date: April 21, 2022
    Inventors: Yuval Inbar, Yossi Gottlieb