Abstract: A method of operating a wire bonding machine is provided. The method includes the steps of: (1) providing a workpiece secured in a bonding position by a device clamp of a wire bonding machine; (2) raising the device clamp to a first height above the workpiece, the device clamp remaining at the first height for a first predetermined period of time; and (3) raising the device clamp to a second height above the workpiece after step (2), the second height being further away from the workpiece than the first height.

Abstract: A method of operating a wire bonding machine is provided. The method includes the steps of: (1) providing a workpiece secured in a bonding position by a device clamp of a wire bonding machine; (2) raising the device clamp to a first height above the workpiece, the device clamp remaining at the first height for a first predetermined period of time; and (3) raising the device clamp to a second height above the workpiece after step (2), the second height being further away from the workpiece than the first height.

Abstract: Methods for etching electrodes formed directly on gate dielectrics are provided. In one aspect, an etch process is provided which includes a main etch step, a soft landing step, and an over etch step. In another aspect, a method is described which includes performing a main etch having good etch rate uniformity and good profile uniformity, performing a soft landing step in which a metal/metal barrier interface can be determined, and performing an over etch step to selectively remove the metal barrier without negatively affecting the dielectric. In another aspect, a method is provided which includes a first non-selective etch chemistry for bulk removal of electrode material, a second intermediate selective etch chemistry with end point capability, and then a selective etch chemistry to stop on the gate dielectric.

Abstract: A method of etching a silicon-containing material in a substrate comprises placing the substrate in a process chamber and exposing the substrate to an energized gas comprising fluorine-containing gas, chlorine-containing gas and sidewall-passivation gas. The silicon-containing material on the substrate comprises regions having different compositions, and the volumetric flow ratio of the fluorine-containing gas, chlorine-containing gas, and sidewall-passivation gas is selected to etch the compositionally different regions at substantially similar etch rates.

Abstract: Methods for etching electrodes formed directly on gate dielectrics are provided. In one aspect, an etch process is provided which includes a main etch step, a soft landing step, and an over etch step. In another aspect, a method is described which includes performing a main etch having good etch rate uniformity and good profile uniformity, performing a soft landing step in which a metal/metal barrier interface can be determined, and performing an over etch step to selectively remove the metal barrier without negatively affecting the dielectric. In another aspect, a method is provided which includes a first non-selective etch chemistry for bulk removal of electrode material, a second intermediate selective etch chemistry with end point capability, and then a selective etch chemistry to stop on the gate dielectric.

Abstract: A two-step method of etching an organic coating layer, in particular, an organic antireflection coating (ARC) layer, is disclosed. During the main etch step, the organic coating layer is etched using a plasma generated from a first source gas which includes a fluorocarbon and a non-carbon-containing, halogen-comprising gas. Etching is performed using a first substrate bias power. During the overetch step, residual organic coating material remaining after the main etch step is removed by exposing the substrate to a plasma generated from a second source gas which includes a chlorine-containing gas and an oxygen-containing gas, and which does not include a polymer-forming gas. The overetch step is performed using a second substrate bias power which is less than the first substrate bias power.

Abstract: A method of forming a notch silicon-containing gate structure is disclosed. This method is particularly useful in forming a T-shaped silicon-containing gate structure. A silicon-containing gate layer is etched to a first desired depth using a plasma generated from a first source gas. During the etch, etch byproducts deposit on upper sidewalls of the silicon-containing gate layer which are exposed during etching, forming a first passivation layer which protects the upper silicon-containing gate layer sidewalls from etching during subsequent processing steps. A relatively high substrate bias power is used during this first etch step to ensure that the passivation layer adheres properly to the upper silicon-containing gate sidewalls.

Abstract: A two-step method of etching an organic coating layer, in particular, an organic antireflection coating (ARC) layer, is disclosed. During the main etch step, the organic coating layer is etched using a plasma generated from a first source gas which includes a fluorocarbon and a non-carbon-containing, halogen-comprising gas. Etching is performed using a first substrate bias power. During the overetch step, residual organic coating material remaining after the main etch step is removed by exposing the substrate to a plasma generated from a second source gas which includes a chlorine-containing gas and an oxygen-containing gas, and which does not include a polymer-forming gas. The overetch step is performed using a second substrate bias power which is less than the first substrate bias power.

Abstract: A method of forming a notched silicon-containing gate structure is disclosed. This method is particularly useful in forming a T-shaped silicon-containing gate structure. A silicon-containing gate layer is etched to a first desired depth using a plasma generated from a first source gas. During the etch, etch byproducts deposit on upper sidewalls of the silicon-containing gate layer which are exposed during etching, forming a first passivation layer which protects the upper silicon-containing gate layer sidewalls from etching during subsequent processing steps. A relatively high substrate bias power is used during this first etch step to ensure that the passivation layer adheres properly to the upper silicon-containing gate sidewalls.