Patents by Inventor Orazio Forlenza
Orazio Forlenza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8086924Abstract: A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.Type: GrantFiled: October 13, 2008Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Phong T Tran
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Patent number: 8065575Abstract: A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating region and each scan chain is unloaded. The ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a failing operating region for the device under test. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.Type: GrantFiled: October 13, 2008Date of Patent: November 22, 2011Assignee: International Business Machines CorporationInventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Phong T Tran
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Patent number: 7921346Abstract: A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.Type: GrantFiled: October 31, 2008Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Bryan J. Robbins, Phong T. Tran
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Publication number: 20100115337Abstract: A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.Type: ApplicationFiled: October 31, 2008Publication date: May 6, 2010Inventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Bryan J. Robbins, Phong T. Tran
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Publication number: 20100095177Abstract: A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.Type: ApplicationFiled: October 13, 2008Publication date: April 15, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Phong T. Tran
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Publication number: 20100095169Abstract: A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating region and each scan chain is unloaded. The ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a failing operating region for the device under test. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.Type: ApplicationFiled: October 13, 2008Publication date: April 15, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Phong T. Tran
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Patent number: 7475308Abstract: A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.Type: GrantFiled: April 11, 2008Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Adrian C. Anderson, Todd Michael Burdine, Donato Orazio Forlenza, Orazio Pasquale Forlenza, William James Hurley, Phong T. Tran
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Publication number: 20080189583Abstract: A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.Type: ApplicationFiled: April 11, 2008Publication date: August 7, 2008Applicant: International Business Machines CorporationInventors: Adrian C. Anderson, Todd Michael Burdine, Donato Orazio Forlenza, Orazio Pasquale Forlenza, William James Hurley, Phong T. Tran
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Patent number: 7395469Abstract: A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.Type: GrantFiled: April 8, 2004Date of Patent: July 1, 2008Assignee: International Business Machines CorporationInventors: Adrian C. Anderson, Todd Michael Burdine, Donato Orazio Forlenza, Orazio Pasquale Forlenza, William James Hurley, Phong T. Tran
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Publication number: 20080091999Abstract: A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.Type: ApplicationFiled: December 14, 2007Publication date: April 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Todd BURDINE, Donato FORLENZA, Orazio FORLENZA, William HURLEY, Phong TRAN
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Publication number: 20070260926Abstract: Exemplary embodiments include a static and dynamic test generation and simulation method including: analyzing a logic model; identifying a logic structure in the logic model whose input/output signal can be assigned to a particular logical value and remain fixed during a fault simulation test; and running the fault simulation test to check the logic model for faults.Type: ApplicationFiled: April 13, 2006Publication date: November 8, 2007Applicant: International Business Machines CorporationInventors: Donato Forlenza, Orazio Forlenza, Mary Kusko
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Patent number: 7225374Abstract: An apparatus, program product and method utilize an ABIST circuit provided on an integrated circuit device to assist in the identification and location of defects in a scan chain that is also provided on the integrated circuit device. In particular, a defect in a scan chain may be detected by applying a plurality of pattern sets to a scan chain coupled to an ABIST circuit, collecting scan out data generated as a result of the application of the plurality of pattern sets to the scan chain, and using the collected scan out data to identify a defective latch in the scan chain.Type: GrantFiled: December 4, 2003Date of Patent: May 29, 2007Assignee: International Business Machines CorporationInventors: Todd Michael Burdine, Donato Orazio Forlenza, Orazio Pasquale Forlenza, William James Hurley, Steven Michnowski, James Bernard Webb
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Publication number: 20070011523Abstract: A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.Type: ApplicationFiled: June 9, 2005Publication date: January 11, 2007Applicant: International Business Machines CorporationInventors: Todd Burdine, Donato Forlenza, Orazio Forlenza, William Hurley, Phong Tran
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Publication number: 20060048028Abstract: A method, apparatus and program product for testing at least one scan chain in an electronic chip in which the scan chain is formed by shift register latches arranged in the chain having a scan path with input pins and output pins. A flush test is executed for the scan chain under test and the flush test diagnostics for the flush test are recorded. A scan test is then executed for the scan chain under test and further test diagnostics are recorded in the event either or both the flush test or the scan test fails. The recorded flush test diagnostics and further test diagnostics are then analyzed to identify a call to one or more probable failed or failing shift register latches in the tested scan chain. The further scan chain diagnostics may include Disturb, Deterministic, ABIST, LBIST and Look-Ahead diagnostics. The tests may also be conducted for different voltage levels to determine the sensitivity of the scan chain being tested to differing voltage levels.Type: ApplicationFiled: September 2, 2004Publication date: March 2, 2006Applicant: International Business Machines CorporationInventors: Charles Blasi, Todd Burdine, Orazio Forlenza
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Publication number: 20050229057Abstract: A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.Type: ApplicationFiled: April 8, 2004Publication date: October 13, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Adrian Anderson, Todd Burdine, Donato Forlenza, Orazio Forlenza, William Hurley, Phong Tran
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Publication number: 20050160339Abstract: Methods and systems for reducing the volume of test data associated with built in self testing (BIST) test methodologies (e.g., logical BIST, array BIST, etc.) and pattern structures are provided. Rather than store the entire set of test parameters for each of a plurality of test sequences to be performed, as with conventional test systems, embodiments of the present invention only store a limited number of “dynamic” test parameters for each test sequence that have changed relative to a previous test sequence.Type: ApplicationFiled: January 15, 2004Publication date: July 21, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Donato Forlenza, Orazio Forlenza, William Hurley, Bryan Robbins
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Publication number: 20050138514Abstract: An apparatus, program product and method utilize an ABIST circuit provided on an integrated circuit device to assist in the identification and location of defects in a scan chain that is also provided on the integrated circuit device. In particular, a defect in a scan chain may be detected by applying a plurality of pattern sets to a scan chain coupled to an ABIST circuit, collecting scan out data generated as a result of the application of the plurality of pattern sets to the scan chain, and using the collected scan out data to identify a defective latch in the scan chain.Type: ApplicationFiled: December 4, 2003Publication date: June 23, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Todd Burdine, Donato Forlenza, Orazio Forlenza, William Hurley, Steven Michnowski, James Webb
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Patent number: 5640402Abstract: A method of effectively reducing a length of shift register (SR) latches used in scan design testing for testing macro structures embedded within very large logic structures eliminates tester hardware buffer limitations required to load and unload a long chain SR. A plurality of shift register latches are connectable in a chain for scan design testing. Each shift register latch is composed of an L1 and an L2 latch receiving A and B clocks, respectively, to shift data into and out of the shift register latch. First specific shift register latches in a chain of shift register latches are used to generate test data inputs to an embedded macro structure, second specific shift register latches in the chain of shift register latches are used to receive test data outputs from the embedded macro structure. A separate B' clock is applied to the L2 latches of the first and second specific shift register latches while maintaining the B clock for the L2 latches for other shift register latches in the chain.Type: GrantFiled: December 8, 1995Date of Patent: June 17, 1997Assignee: International Business Machines CorporationInventors: Franco Motika, Donato Orazio Forlenza, Adrian Charles Anderson