Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.

Abstract: A processing unit, where the processing unit one of a group of processing units of a system, includes a processor; and memory including instructions, which when executed by the processor while avoiding interrupting a controller that does not belong to the group of processing units, cause the processor to: perform at least one iteration of the steps of: (a) entering a trusted mode, (b) selecting a selected job to be executed by the processing unit, (c) retrieving access control metadata related to the selected job, (d) entering, by the processing unit, an untrusted mode, (e) executing the selected job by the processing unit while adhering to the access control metadata related to the job, and (f) resetting the processing unit.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

Abstract: A processing unit, where the processing unit one of a group of processing units of a system, includes a processor; and memory including instructions, which when executed by the processor while avoiding interrupting a controller that does not belong to the group of processing units, cause the processor to: perform at least one iteration of the steps of: (a) entering a trusted mode, (b) selecting a selected job to be executed by the processing unit, (c) retrieving access control metadata related to the selected job, (d) entering, by the processing unit, an untrusted mode, (e) executing the selected job by the processing unit while adhering to the access control metadata related to the job, and (f) resetting the processing unit.

Abstract: A method for retrieving neural network coefficients may include executing neural network operations and storing, in at least one data memory, one or more intermediate results of the neural network operations. The method may also include retrieving, in an iterative manner, subsets of neural network coefficients related to a particular layer of a neural network associated with at least one of the neural network processors. Different ones of the neural network processors may use at least one of the subsets of the neural network coefficients. The retrieving the subsets of neural network coefficients may include caching the subsets in coefficient cache memory. At least some of the subsets may be cached in the coefficient cache memory for up to a first duration, and at least some of the intermediate results may be stored in the at least one data memory for a duration that exceeds the first duration.

Abstract: A method for executing atomic commands may include receiving, by an interface of an atomic command execution unit and from a plurality of requestors, a plurality of memory mapped atomic commands. The method may also include executing the plurality of memory mapped atomic commands to provide output values. The method may further include storing, in a first memory unit of the atomic command execution unit, requestor specific information. Different entries of a plurality of entries of the first memory unit may be allocated to different requestors of the plurality of requestors. The method may also include storing, in a second memory unit of the atomic command execution unit, the output values of the plurality of memory mapped atomic commands, and outputting, by the interface and to at least one of the plurality of requestors, at least one indication indicating a completion of at least one of the atomic commands.

Abstract: A method for decompressing data may include receiving a first sequence of bits and performing a plurality of iterations. Each of the plurality of iterations may include scanning bits of the first sequence, starting from a starting point, to search for at least one of a variable length codeword or a bypass indicator, the starting point being either a starting point of the first sequence or a starting point defined in a previous iteration. The method also include, for at least one of the plurality of iterations, when a bypass indicator is found, outputting a neural network coefficient related value (NNCRV) that is non-compressed and follows the bypass indicator, and defining a starting point that follows the NNCRV as a starting point for a next iteration.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.

Abstract: A processing unit, where the processing unit one of a group of processing units of a system, includes a processor; and memory including instructions, which when executed by the processor while avoiding interrupting a controller that does not belong to the group of processing units, cause the processor to: perform at least one iteration of the steps of: (a) entering a trusted mode, (b) selecting a selected job to be executed by the processing unit, (c) retrieving access control metadata related to the selected job, (d) entering, by the processing unit, an untrusted mode, (e) executing the selected job by the processing unit while adhering to the access control metadata related to the job, and (f) resetting the processing unit.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.

Abstract: Embodiments described herein provide a processing apparatus comprising compute logic to generate output feature map data for a convolutional neural network (CNN) and write the feature map data to a memory buffer; a direct memory access (DMA) controller including a feature map encoder, the DMA controller to read the feature map data from the memory buffer, encode the feature map data using one of multiple encode algorithms, and write encoded feature map data to memory coupled with the processing apparatus; and wherein the compute logic is to read the encoded feature map data from the memory in an encoded format and decode the encoded feature map data while reading the encoded feature map data.

Abstract: An apparatus includes a communication processor to receive configuration information from a producing compute building block; a credit generator to generate a number of credits for the producing compute building block corresponding to the configuration information, the configuration information including characteristics of a buffer; a source identifier to analyze a returned credit to determine whether the returned credit originates from the producing compute building block or a consuming compute building block; and a duplicator to, when the returned credit originates from the producing compute building block, multiply the returned credit by a first factor, the first factor indicative of a number of consuming compute building blocks identified in the configuration information.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable dynamic processing of a predefined workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to obtain a workload node, the workload node associated with a first amount of data, the workload node to be executed at a first one of the one or more computational building blocks; an analyzer to: determine whether the workload node is a candidate for early termination; and in response to determining that the workload node is a candidate for early termination, set a flag associated with a tile of the first amount of data; and a dispatcher to, in response to the tile being transmitted from the first one of the one or more computational building blocks to a buffer, stop execution of the workload node.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

Abstract: Embodiments described herein provide a processing apparatus comprising compute logic to generate output feature map data for a convolutional neural network (CNN) and write the feature map data to a memory buffer; a direct memory access (DMA) controller including a feature map encoder, the DMA controller to read the feature map data from the memory buffer, encode the feature map data using one of multiple encode algorithms, and write encoded feature map data to memory coupled with the processing apparatus; and wherein the compute logic is to read the encoded feature map data from the memory in an encoded format and decode the encoded feature map data while reading the encoded feature map data.

Abstract: A method to divide a database of TCAM rules includes selecting a rule of the database having multiple don't care values and selecting a bit of the rule having a don't care value, generating two distributor rules based on the selected rule, where the selected bit has a 1 value in one of the distributor rules and a 0 in the other of the distributor rules, associating rules of the database which match each of the distributor rules with the distributor rule they match thereby to create associated databases, and repeating the steps of selecting, generating and associating on the database and the associated databases until the average number of rules in each associated database is at or below a predefined amount. A search unit includes a distributor TCAM and a DRAM search unit having a DRAM storage unit and an associated DRAM search logic unit. The DRAM storage unit has a section for each associated database, where each section is pointed to by a different distributor rule.

Abstract: A search unit including a distributor TCAM and a DRAM search unit and a method to divide a database of TCAM rules is disclosed. The method includes selecting a rule having multiple “don't care” values and selecting a bit of the rule having a “don't care” value, generating two distributor rules based on the selected rule, associating rules of the database which match each of the distributor rules with the distributor rule they match to create subset databases, and repeating the steps of selecting, generating and associating until the average number of rules in each subset database is at or below a predefined amount. A DRAM storage unit has a section for each subset database, where each section is pointed to by a different distributor rule. A DRAM search unit matches an input key to one of the rules in the section pointed to by the matched distributor rule.

Abstract: A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time, thereby to generate a Boolean function output of the data of the at least two cells, wherein each of the at least two cells includes at least a storage capacitor, a storage transistor and a read line, where the storage transistor is connected to the read line and subject to activation by a charge in the storage capacitor.