Abstract: This disclosure describes a Chroma-based video converter that includes a first interface that receives the video signal to be encoded. The converter includes a frame splitter configured to receive one or more RGB frames, the frame splitter splits the RGB frame into R data, G data, and B data. The converter further includes a framing module configured to convert the received RGB frame into a first YUV frame and a second YUV frame. The converter additional includes an encoder configured to encode the first YUV frame and the second YUV frame based on a timestamp as that associated with the RGB frame. The converter further includes a multiplexer configured to multiplex the encoded first YUV frame and the encoded second YUV frame to generate a single encoded signal. And, the converter includes a second interface that transmits the generated single encoded video signal.

Abstract: A method of DRM protection for an image or a series of images or a succession of video frames, comprises: generating a reversible transform; applying the reversible transform to a source image; compressing the transformed image into a bitstream; and supplying the bitstream to a recipient for consumption. At the recipient the bitstream is decompressed and sent to the image display hardware with the transform still in place. A key is used to generate the inverse transform at the recipient and the inverse transform is then carried out in the image display hardware. An additional transform may be applied to the image following the inverse transform to offset pixels from an average value. Thus the source image itself is never exposed at the recipient although the image can be correctly viewed.

Abstract: This disclosure describes a computer-implemented method for a control mechanism for video output. Additionally provided is a video stream that is generated from the video source and encoded by the video encoder, where the video stream further comprises one or more video frames with each video frame including a time stamp that includes timing and clocking information. Additionally provided is a video display apparatus that includes a video display apparatus processor, video display apparatus memory, video decoder, and a video frame buffer, where the video decoder decodes the encoded video stream, and the video display apparatus generates a pixel clock. Additionally provided is a desired latency threshold for displaying a first video frame with respect to a second video frame that includes an upper threshold limit and a lower threshold limit. The disclosed method includes the following steps that control jitter in the displayed video stream.

Abstract: This disclosure describes an apparatus (106) for improving performance of a multipoint control unit (210). The apparatus (106) provides a video stream manipulator (208) and a multipoint control unit (210). The video stream manipulator (208) may encode one or more video streams in a predetermined video codec standard separately. Each of the encoded video streams includes at least one encoded video frame made of a plurality of macroblocks, where the macroblocks are segregated into a predetermined number of macroblock lines. The multipoint control unit (210) may assemble predetermined number of macroblock lines from each of the encoded video streams in a predetermined composition.

Abstract: A method of verifying, controlling and limiting distribution of digital artwork files, comprises designating a trusted third party registration server; receiving a digital artwork; registering the received artwork at the registration server; defining an allowed number of copies of the registered artwork, the allowed number being at least one; creating individual copies of the artwork up to the allowed number; at the registration server assigning an individual copy to a user; supplying the user with a file comprising an electronically watermarked version of the individual copy; allowing the user to relinquish the individual copy; upon relinquishing, making the individual copy available to a second user by repeating the supplying stage.

Abstract: A method of DRM protection for an image or a series of images or a succession of video frames, comprises: generating a reversible transform; applying the reversible transform to a source image; compressing the transformed image into a bitstream; and supplying the bitstream to a recipient for consumption. At the recipient the bitstream is decompressed and sent to the image display hardware with the transform still in place. A key is used to generate the inverse transform at the recipient and the inverse transform is then carried out in the image display hardware. An additional transform may be applied to the image following the inverse transform to offset pixels from an average value. Thus the source image itself is never exposed at the recipient although the image can be correctly viewed.

Abstract: This disclosure describes a computer-implemented method for a control mechanism for video output. Additionally provided is a video stream that is generated from the video source and encoded by the video encoder, where the video stream further comprises one or more video frames with each video frame including a time stamp that includes timing and clocking information. Additionally provided is a video display apparatus that includes a video display apparatus processor, video display apparatus memory, video decoder, and a video frame buffer, where the video decoder decodes the encoded video stream, and the video display apparatus generates a pixel clock. Additionally provided is a desired latency threshold for displaying a first video frame with respect to a second video frame that includes an upper threshold limit and a lower threshold limit. The disclosed method includes the following steps that control jitter in the displayed video stream.

Abstract: This disclosure describes an external video locking and synchronization device (104) in communication with a video source (102) and a target device (106). The external video locking and synchronization device (104) provides a video receiver (202), a memory (208), and a locking and synchronization circuitry (204). The video receiver (202) receives a video signal from the video source (102). The video signal has one or more video frames, each being associated with clocking information and frame synchronization information. The memory (208) is in communication with the video receiver (202) and stores the clocking information and the frame synchronization information. The locking and synchronization circuitry (204) adjusts vertical frequency of the video signal by a predetermined value; and generates a synchronized video signal for the target device (106), where the synchronized video signal is locked into the video signal.

Abstract: This disclosure describes an apparatus (106) for improving performance of a multipoint control unit (210). The apparatus (106) provides a video stream manipulator (208) and a multipoint control unit (210). The video stream manipulator (208) may encode one or more video streams in a predetermined video codec standard separately. Each of the encoded video streams includes at least one encoded video frame made of a plurality of macroblocks, where the macroblocks are segregated into a predetermined number of macroblock lines. The multipoint control unit (210) may assemble predetermined number of macroblock lines from each of the encoded video streams in a predetermined composition.