Abstract: IC apparatus, and manufacturing methods therefor, that include a power transistor and a thermoelectric device. The power transistor is constructed in a plurality of layers formed over a semiconductor substrate. The thermoelectric device is formed in one or more of the plurality of layers and is sensitive to temperature differences within the IC apparatus resulting from operation of the power transistor.

Abstract: An electronic device has a first circuit, a second circuit, and an isolation circuit, the isolation circuit having an input and an output, the first circuit including a signal generator having an output, the output of the signal generator coupled to the input of the isolation circuit. The second circuit includes a rectifier circuit and a signal detector circuit, the rectifier circuit having a rectifier input coupled to the output of the isolation circuit, and the signal detector circuit having an input coupled to the output of the isolation circuit.

Abstract: A power transistor includes an ambient temperature input, a local temperature sensor, an array of transistor cells, and a thermal feedback circuit. The ambient temperature input is configured to receive an ambient temperature signal that is representative of an ambient temperature of the power transistor. The array of transistor cells has a control input. The local temperature sensor is configured to provide a local temperature signal that is representative of a temperature of the array of transistor cells. The thermal feedback circuit is coupled to the ambient temperature input, the local temperature sensor, and the control input. The thermal feedback circuit is configured to modulate a control signal provided at the control input based on a difference between the ambient temperature signal and the local temperature signal.

Abstract: Examples of this description include providing a first control signal having an asserted value at a first control terminal of a controllable resistive element at a first time. Examples of this description also include providing a second control signal having an asserted value at a control terminal of a high-side power transistor of a power converter subsequent to providing the first control signal, wherein the controllable resistive element snubs the high-side power transistor.

Abstract: The present disclosure generally relates to biasing an isolation region in a semiconductor substrate. In an example, an integrated circuit includes a semiconductor substrate, a first rectifying device, and a second rectifying device. The semiconductor substrate has a first region, a second region, and a third region each being an opposite conductivity type from the semiconductor substrate. The first region and the second region are respective current terminals of a transistor. The first rectifying device has a first positive terminal and a first negative terminal. The first positive terminal is coupled to the first region, and the first negative terminal is coupled to the third region. The second rectifying device has a second positive terminal and a second negative terminal. The second positive terminal is coupled to a ground terminal, and the second negative terminal is coupled to the third region.

Abstract: In one example, an apparatus comprises: a first transistor coupled between a power terminal and a switching terminal; a second transistor coupled between the power terminal and a first sense terminal; a third transistor coupled between the switching terminal and a ground terminal; a fourth transistor coupled between a second sense terminal and the ground terminal; a first variable current source coupled to the first sense terminal; a second variable current source coupled to the second sense terminal; a processing circuit having first, second, third, and fourth inputs and first and second outputs, the first input coupled to the switching terminal, the second input coupled to the first sense terminal, the third input coupled to the ground terminal, the fourth input coupled to the second sense terminal, the first output coupled to the first variable current source, and the second output coupled to the second variable current source.

Abstract: IC apparatus, and manufacturing methods therefor, that include a power transistor and a thermoelectric device. The power transistor is constructed in a plurality of layers formed over a semiconductor substrate. The thermoelectric device is formed in one or more of the plurality of layers and is sensitive to temperature differences within the IC apparatus resulting from operation of the power transistor.

Abstract: Integrated circuit apparatus, and their manufacturing methods, including an integrated power transistor and thermocouple. The power transistor is constructed in a plurality of layers formed over a semiconductor substrate. The thermocouple includes a p-thermopile and an n-thermopile that are each electrically isolated from the power transistor and the semiconductor substrate while being sensitive to temperature differences within the IC resulting from operation of the power transistor. The p-thermopile includes a p-type thermoelectric body formed in a p-type one or more of the plurality of layers. The n-thermopile includes n-type thermoelectric body formed in an n-type one or more of the plurality of layers.

Abstract: A method includes charging a capacitor of a power inverter to a direct current (DC) input voltage from an input terminal of the power inverter. The capacitor has first and second terminals. The method also includes providing a first voltage at an output terminal of the power inverter at a first time by controlling one of either: an output switch that selectively couples the output terminal to either the first terminal or the second terminal; or a set of input switches that selectively couple the first and second terminals to either the input terminal or a ground terminal. The method further includes providing a second voltage at the output terminal at a second time by controlling the other of the output switch or the set of input switches.

Abstract: A switched capacitor voltage multiplication device has a rectifier with a DC input terminal and a DC output terminal and two pulse input terminals. A first flying capacitor is coupled to one of the pulse input terminals, while a second flying capacitor is coupled to the other pulse input terminal. A recycle resistor is coupled across the rectifier with a first resistor terminal coupled to one pulse input terminal and a second resistor terminal coupled to the other pulse input terminal.

Abstract: An example apparatus includes: a gate driver with a control output terminal, a power transistor with a gate terminal and a first current terminal, the gate terminal coupled to the control output terminal, and drain-derived supply circuitry with an output coupled to the first current terminal.

Abstract: An electronic device has a first circuit, a second circuit, and an isolation circuit, the isolation circuit having an input and an output, the first circuit including a signal generator having an output, the output of the signal generator coupled to the input of the isolation circuit. The second circuit includes a rectifier circuit and a signal detector circuit, the rectifier circuit having a rectifier input coupled to the output of the isolation circuit, and the signal detector circuit having an input coupled to the output of the isolation circuit.

Abstract: A system includes a power receiver including an oscillator with a first coil and a second coil. The oscillator includes a first field effect transistor (FET) having first gate, first source, and first drain terminals, the first drain terminal coupled to the first coil, the first coil adapted to be inductively coupled to a third coil in a power transmitter. The oscillator also includes a first capacitor coupled to the first coil. The oscillator includes a second FET having second gate, second source, and second drain terminals, the second gate terminal coupled to the first capacitor, the second source terminal coupled to the first source terminal, and the second drain terminal coupled to the second coil, the second coil adapted to be inductively coupled to a fourth coil in the power transmitter. The oscillator includes a second capacitor coupled to the first gate terminal and coupled to the second coil.

Abstract: A method includes charging a capacitor of a power inverter to a direct current (DC) input voltage provided at an input terminal of the power inverter. The capacitor has a first terminal and a second terminal. The method also includes providing a first voltage at an output terminal of the power inverter at a first time by controlling one of either a set of input switches configured to selectively couple the first and second terminals to either the input terminal or to a ground terminal, or an output switch configured to selectively couple the output terminal to either the first terminal or the second terminal. The method further includes providing a second voltage at the output terminal at a second time by controlling the other of the set of input switches and the output switch.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes an amplifier having a first input configured to receive a signal representative of a condition related to a power converter, a second input configured to receive a reference signal, and an output, a PWM regulation circuit having an input coupled to the output of the amplifier, a first output configured to provide a first control signal for a high-side transistor of the power converter, and a second output configured to output a first control signal for a low-side transistor of the power converter, and a PFM regulation circuit having an input coupled to the output of the first amplifier, a first output configured to output a second control signal for the high-side transistor of the power converter, and a second output configured to output a second control signal for the low-side transistor of the power converter.

Abstract: In described examples of methods and control circuitry to control a multi-level power conversion system, the control circuitry generates PWM signals having a duty cycle to control an output signal. The duty cycle is adjustable in different switching cycles. States of the system's switches are adjustable in one or more intervals within the switching cycles. In response to a voltage across a capacitor of the system being outside a non-zero voltage range, the control circuitry adjusts states of the switches in two intervals to discharge or charge the capacitor in a given switching cycle.

Abstract: In a described example, a circuit includes a power device having voltage inputs and a command input. A sensing circuit has a sensor input and a sensor output, in which the sensor input is coupled to the power device. A control circuit has a control input and a control output, in which the control input coupled to the sensor output. A driver circuit has a driver input and a driver output. The driver input is coupled to the control output, and the driver output is coupled to the command input of the power device.

Abstract: A system includes a power receiver including an oscillator with a first coil and a second coil. The oscillator includes a first field effect transistor (FET) having first gate, first source, and first drain terminals, the first drain terminal coupled to the first coil, the first coil adapted to be inductively coupled to a third coil in a power transmitter. The oscillator also includes a first capacitor coupled to the first coil. The oscillator includes a second FET having second gate, second source, and second drain terminals, the second gate terminal coupled to the first capacitor, the second source terminal coupled to the first source terminal, and the second drain terminal coupled to the second coil, the second coil adapted to be inductively coupled to a fourth coil in the power transmitter. The oscillator includes a second capacitor coupled to the first gate terminal and coupled to the second coil.

Abstract: Aspects of the disclosure include a first sense transistor having a gate and a drain configured to couple in parallel with a high-side transistor and a source terminal coupled to a first node, and a second sense transistor having a gate and a drain configured to couple in parallel with a low-side transistor, and a source terminal coupled to a third node. The circuit further includes a first comparator circuit having a first input coupled to the first node, a second input coupled to a second node, and an output, a second comparator circuit having a first input coupled to the third node, a second input coupled to a ground node, and an output, and a logic circuit having first input coupled to the output of the first comparator circuit, a second input coupled to the output of the second comparator circuit, and an output.

Abstract: In a described example, an apparatus includes a first switch coupled between a terminal for receiving an input voltage and a top plate node, and having a first control terminal; a second switch coupled between the top plate node and a switching node, and having a second control terminal; a third switch coupled between the switching node and a bottom plate node and having a third control terminal; a fourth switch coupled between the bottom plate node and a ground terminal, and having a fourth control terminal; a flying capacitor coupled between the top plate node and the bottom plate node; a fifth switch coupled between the top plate node and an auxiliary node; a sixth switch coupled between the auxiliary node and the bottom plate node; and an auxiliary capacitor coupled between the auxiliary control terminal and a ground terminal.