Abstract: A network device includes a first interface, a second interface, and circuitry. The first interface is configured to communicate at least with a memory. The second interface is configured to communicate over a network with a peer network device. The circuitry is configured to receive a request to transfer data over the network between the memory and the peer network device in accordance with (i) a pattern of offsets to be accessed in the memory and (ii) a memory key representing a memory space to be accessed using the pattern, and to transfer the data in accordance with the request.

Abstract: A network device includes a first interface, a second interface and circuitry. The first interface is configured to communicate at least with a first memory. The second interface is configured to communicate over a network with a peer network device coupled to a second memory. The circuitry is configured to (i) receive a request to transfer data over the network between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.

Abstract: A Direct Memory Access (DMA) device includes an interface and a DMA engine. The interface is configured to communicate with a first memory and with a second memory. The DMA engine is configured to (i) receive a request to transfer data between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.

Abstract: A networking device and system are described, among other things. An illustrative system is disclosed to include a packet parser and a state machine that includes a NULL header state. The packet parser references the state machine to enter the NULL header state automatically in response to parsing a packet header of a predetermined type and then, while in the NULL header state, analyzes a subsequent set of bytes without advancing a parser pointer.

Abstract: A system, switch device, and method of operating a switch device are provided. An illustrative system is disclosed to include a first router block configured to receive a first type of Remote Direct Memory Access (RDMA) packet, a second router block configured to receive a second type of RDMA packet, and a gateway positioned between the first router block and the second router block. The gateway may be configured to translate the first type of RDMA packet received from the first router block for transmission as the second type of RDMA packet by the second router block.

Abstract: A system, switch device, and method of operating a switch device are provided. An illustrative system is disclosed to include a first router block configured to receive a first type of Remote Direct Memory Access (RDMA) packet, a second router block configured to receive a second type of RDMA packet, and a gateway positioned between the first router block and the second router block. The gateway may be configured to translate the first type of RDMA packet received from the first router block for transmission as the second type of RDMA packet by the second router block.

Abstract: A network element includes a plurality of ports, multiple computational modules, configurable forwarding circuitry and a central block. The ports include child ports coupled to child network elements or network nodes and parent ports coupled to parent network elements. The computational modules collectively perform a data reduction operation of a data reduction protocol. The forwarding circuitry interconnects among ports and computational modules. The central block receives a request indicative of child ports, a parent port, and computational modules required for performing reduction operations on data received via the child ports, for producing reduced data destined to the parent port, to derive from the request a topology that interconnects among the child ports, parent port and computational modules for performing the data reduction operations and to forward the reduced data for transmission to the selected parent port, and to configure the forwarding circuitry to apply the topology.

Abstract: A network element includes a plurality of ports, multiple computational modules, configurable forwarding circuitry and a central block. The ports include child ports coupled to child network elements or network nodes and parent ports coupled to parent network elements. The computational modules collectively perform a data reduction operation of a data reduction protocol. The forwarding circuitry interconnects among ports and computational modules. The central block receives a request indicative of child ports, a parent port, and computational modules required for performing reduction operations on data received via the child ports, for producing reduced data destined to the parent port, to derive from the request a topology that interconnects among the child ports, parent port and computational modules for performing the data reduction operations and to forward the reduced data for transmission to the selected parent port, and to configure the forwarding circuitry to apply the topology.

Abstract: Communication apparatus includes multiple interfaces configured to be connected to a network so as to receive and transmit data packets having respective packet headers, which can include sub-headers of different, respective types. A memory stores instructions for parsing each type of sub-headers and a transition table, which indicates, for each of the types, a location of the instructions for parsing a subsequent sub-header depending upon the type of the subsequent sub-header. A plurality of predefined types are represented in the transition table by a common alias. Routing logic parses the first sub-header in a packet, reads the type of the second sub-header from the first sub-header, and accesses the transition table using the common alias in place of the type of the first sub-header so as to locate and read the instructions for parsing the second sub-header.

Abstract: Communication apparatus includes multiple interfaces configured to be connected to a network so as to receive and transmit data packets having respective packet headers that includes a basic header record and one or more optional records. Parsing instructions specify one or more types of the optional records and indicate, for each specified type, an offset within an optional record of the specified type. Upon receiving each packet, routing logic parses the basic header record in the packet, parses the one or more optional records so as to identify any optional records of the one or more specified types, extracts header data from the identified optional records at the offset indicated for the specified type, and processes and forwards the data packets via the interfaces to the network in accordance with information parsed from the basic header record and the extracted header data.

Abstract: Communication apparatus includes multiple interfaces configured to be connected to a network so as to receive and transmit data packets having respective packet headers that includes a basic header record and one or more optional records. Parsing instructions specify one or more types of the optional records and indicate, for each specified type, an offset within an optional record of the specified type. Upon receiving each packet, routing logic parses the basic header record in the packet, parses the one or more optional records so as to identify any optional records of the one or more specified types, extracts header data from the identified optional records at the offset indicated for the specified type, and processes and forwards the data packets via the interfaces to the network in accordance with information parsed from the basic header record and the extracted header data.

Abstract: Communication apparatus includes multiple interfaces configured to be connected to a network so as to receive and transmit data packets having respective packet headers, which can include sub-headers of different, respective types. A memory stores instructions for parsing each type of sub-headers and a transition table, which indicates, for each of the types, a location of the instructions for parsing a subsequent sub-header depending upon the type of the subsequent sub-header. A plurality of predefined types are represented in the transition table by a common alias. Routing logic parses the first sub-header in a packet, reads the type of the second sub-header from the first sub-header, and accesses the transition table using the common alias in place of the type of the first sub-header so as to locate and read the instructions for parsing the second sub-header.