Abstract: A printed wiring board includes a first insulating layer, a first conductor circuit including fingerprint authentication circuitry and embedded in the first insulating layer such that the first circuit has exposed surface exposed from surface of the first insulating layer, a second insulating layer on which the first insulating layer is formed, a second conductor circuit including fingerprint authentication circuitry and embedded in the second insulating layer such that the second circuit has exposed surface exposed from surface of the second insulating layer and is interposed between the first and second insulating layers, and a solder resist layer formed on the surface of the first insulating layer and covering the first circuit. The first and second circuits are positioned such that the first and second circuits are opposing each other across the first insulating layer and that a finger for fingerprint authentication is placed on the solder resist layer.

Abstract: A package substrate includes an outermost interlayer, an outermost conductive layer including first pads positioned to mount at electronic component and second pads positioned to mount another electronic component, a first conductive layer including first circuits and formed such that the outermost interlayer is on the first conductive layer and that the first circuits are connecting the first and second pads, an inner interlayer formed such that the first conductive layer is on the inner interlayer, a second conductive layer formed such that the inner interlayer is on the second conductive layer, via conductors penetrating through the outermost interlayer and including first via conductors connecting the first conductive layer and the first pads and second via conductors connecting the first conductive layer and the second pads, and third via conductors penetrating through the inner interlayer and positioned such that the first and third via conductors form stacked via conductors.

Abstract: A printed wiring board includes a first insulating layer, a first conductor circuit including fingerprint authentication circuitry and embedded in the first insulating layer such that the first circuit has exposed surface exposed from surface of the first insulating layer, a second insulating layer on which the first insulating layer is formed, a second conductor circuit including fingerprint authentication circuitry and embedded in the second insulating layer such that the second circuit has exposed surface exposed from surface of the second insulating layer and is interposed between the first and second insulating layers, and a solder resist layer formed on the surface of the first insulating layer and covering the first circuit. The first and second circuits are positioned such that the first and second circuits are opposing each other across the first insulating layer and that a finger for fingerprint authentication is placed on the solder resist layer.

Abstract: A package substrate includes resin insulating interlayers, and four or more conductive layers including dedicated wiring layers such that the dedicated wiring layers are two dedicated wiring layers which transmit data between a first electronic component and a second electronic component connected by the two dedicated wiring layers.

Abstract: A package substrate includes an outermost interlayer, an outermost conductive layer including first pads positioned to mount at electronic component and second pads positioned to mount another electronic component, a first conductive layer including first circuits and formed such that the outermost interlayer is on the first conductive layer and that the first circuits are connecting the first and second pads, an inner interlayer formed such that the first conductive layer is on the inner interlayer, a second conductive layer formed such that the inner interlayer is on the second conductive layer, via conductors penetrating through the outermost interlayer and including first via conductors connecting the first conductive layer and the first pads and second via conductors connecting the first conductive layer and the second pads, and third via conductors penetrating through the inner interlayer and positioned such that the first and third via conductors form stacked via conductors.