Abstract: A layout designing apparatus and a layout designing method that can improve the uniformity of the pattern density of a layout pattern in which dummy patterns are formed, and a semiconductor device manufactured using the layout designing method can be obtained. The layout designing method includes the steps of entering a plurality of circuit patterns of a semiconductor device; recognizing the positional data of the entered plurality of circuit patterns; producing a dummy pattern group including a plurality of dummy patterns, each of which being arranged per repetitive distance determined based on the recognized positional data of the circuit patterns; extracting a final dummy pattern including a dummy pattern located in a region not overlapping with the circuit patterns from the dummy pattern group; and outputting a layout pattern including the extracted final dummy pattern and the circuit patterns.

Abstract: A semiconductor integrated circuit layout figure, inclusive of dimensional accuracy depending on the pattern shape, is efficiently verified with high accuracy. A layout verifying method for verifying whether or not a layout figure conforms to a design rule on the basis of vector data includes a reference vector classifying step for selecting and classifying a reference vector which serves as a reference for verification among vectors corresponding to sides, a verification object vector classifying step for selecting and classifying a object vector to be verified among the vectors corresponding to the sides and a verifying step for verifying a distance between each reference vector and the object vector to be verified selected among the vectors to be verified classified in correspondence with the direction of the reference vector.

Abstract: A layout designing apparatus and a layout designing method that can improve the uniformity of the pattern density of a layout pattern in which dummy patterns are formed, and a semiconductor device manufactured using the layout designing method can be obtained. The layout designing method includes the steps of entering a plurality of circuit patterns of a semiconductor device; recognizing the positional data of the entered plurality of circuit patterns; producing a dummy pattern group including a plurality of dummy patterns, each of which being arranged per repetitive distance determined based on the recognized positional data of the circuit patterns; extracting a final dummy pattern including a dummy pattern located in a region not overlapping with the circuit patterns from the dummy pattern group; and outputting a layout pattern including the extracted final dummy pattern and the circuit patterns.