Abstract: Disclosed is a wafer-scale chip structure including a semiconductor wafer and multiple dies on the semiconductor wafer. The dies can include at least two dies with different patterns of fill shapes. Also disclosed are wafer-scale chip design methods and systems. In the design methods and systems, post-chip layout wafer-level topography optimization is performed to, for example, minimize performance variations between dies of the same design within the wafer-scale chip. Specifically, across-wafer die placement and wafer-level topography information is used to custom design and/or select different patterns of fill shapes to be inserted into the layouts of dies placed at different locations across the wafer-scale chip (including different patterns to be inserted into the layouts of dies that have the same design) in order to generate a design that minimizes either all across-wafer thickness variations or at least across-wafer thickness variations associated with specific dies having the same specific design.

Abstract: A system and method to model and design a layout of an Internet Datacenter (IDC) for cooling. The IDC is defined as a collection of cells, the cells of the IDC are pre-characterized, an arrangement of the cells within the IDC is determined, and a profile for one or more parameters of interest for each cell are determined.

Abstract: A system and method to reduce leakage power consumption of electronic devices. In addition to assigning threshold voltages, sizes of the transistors within the device may be varied to provide a range of options to meet the timing requirements while minimizing the leakage power consumption.

Abstract: A method or process of manufacturing on-chip bypass capacitors on a VLSI device (or chip) is improved by utilizing a high-dielectric constant metal-insulator-metal (MIM) capacitor manufacturing process. The high-k constant MIM capacitor may include a lower electrode in a first metal layer of a VLSI device, a substantially thin layer of high-k insulator (e.g., silicon nitride at an interface of the first metal layer and a via, and an upper electrode form in a second metal layer. The via provides a channel between the second metal layer to the high-k insulator.

Abstract: A method reduces noise resulting from a current surge in a circuit. A plurality of loading elements, parallel with the circuit being protected, are connected sequentially and disconnected. The connection of the loading elements results in a ramping up of current through the circuit without a sudden surge. In a preferred embodiment, an apparatus for slowing a current change in a circuit is described. The apparatus comprises a plurality of loading elements placed in parallel with the circuit, each of the elements providing a path for current flow, and a control circuit for selectively opening or closing at least one of said paths to prevent or enable current flow through the at least one of the paths.

Abstract: A logic gate circuit and related methods and apparatus exhibit reduced voltage swing and thereby consume less power. The circuit is connected to a plurality of input signals and a clock signal. The circuit produces an output. The circuit comprises a node, a pull-down network and an N-type MOS transistor. The pull-down network is connected to the node, a first reference voltage, the plurality of inputs and the clock signal. The N-type MOS transistor is connected between the node and a second reference voltage. The N-type MOS transistor is also connected to a complement of the clock signal. A method of the invention accepts a complement of a clock signal and pre-charges a node to a voltage less than a power supply voltage, in response to the complement of the clock signal. The method also accepts a plurality of input signals and accepts the clock signal. The method conditionally discharges the node, in response to the clock signal, on the basis of the plurality of input signals.

Abstract: A system and method to reduce leakage power consumption of electronic devices. In addition to assigning threshold voltages, sizes of the transistors within the device may be varied to provide a range of options to meet the timing requirements while minimizing the leakage power consumption.

Abstract: A system and method to model and design a layout of an Internet Datacenter (IDC) for cooling. The IDC is defined as a collection of cells, the cells of the IDC are pre-characterized, an arrangement of the cells within the IDC is determined, and a profile for one or more parameters of interest for each cell are determined.

Abstract: A method reduces noise resulting from a current surge in a circuit. A plurality of loading elements, parallel with the circuit being protected, are connected sequentially and disconnected. The connection of the loading elements results in a ramping up of current through the circuit without a sudden surge. In a preferred embodiment, an apparatus for slowing a current change in a circuit is described. The apparatus comprises a plurality of loading elements placed in parallel with the circuit, each of the elements providing a path for current flow, and a control circuit for selectively opening or closing at least one of said paths to prevent or enable current flow through the at least one of the paths.

Abstract: An RLC module is configured to provide a simplified circuit modeling of a selected circuit net (or portion) of an electronic circuit. The RLC module may be configured to substitute an RLC circuit model for the selected circuit net, where the effective values of the capacitance and inductance for the RLC circuit model are retrieved from a table of capacitance and inductance values. A set of interconnect geometry factors (e.g., line length, line width, driver/receiver length, etc.) that describes the circuit net is used as an index into the table of capacitance and inductance values. The retrieved values of the effective capacitance and inductances values may be used to calculate a delay for the RLC circuit model. The RLC module may provide the capability to quickly calculate a delay for a selected circuit net without using computationally intensive calculations for inductance and capacitance values of circuit nets.

Abstract: Power surges in electrical systems, such as microprocessors, may be reduced by gradually applying power to resources, such as the floating point unit, to an active state. Also, performance penalty may be minimized by predicting ahead of time when a resource will be needed. In this manner, the power to the resource may be gradually applied so that the resource is active when it is actually needed. Modules may be included that predicts when a resource is needed based on instructions prefetched instruction from a pipeline of a microprocessor. Based on the prediction, power control modules may control the power to the necessary resource gradually.

Abstract: An RLC module is configured to provide a simplified circuit modeling of a selected circuit net (or portion) of an electronic circuit. The RLC module may be configured to substitute an RLC circuit model for the selected circuit net, where the effective values of the capacitance and inductance for the RLC circuit model are retrieved from a table of capacitance and inductance values. A set of interconnect geometry factors (e.g., line length, line width, driver/receiver length, etc.) that describes the circuit net is used as an index into the table of capacitance and inductance values. The retrieved values of the effective capacitance and inductances values may be used to calculate a delay for the RLC circuit model. The RLC module may provide the capability to quickly calculate a delay for a selected circuit net without using computationally intensive calculations for inductance and capacitance values of circuit nets.

Abstract: A logic gate circuit and related methods and apparatus exhibit reduced voltage swing and thereby consume less power. The circuit is connected to a plurality of input signals and a clock signal. The circuit produces an output. The circuit comprises a node, a pull-down network and an N-type CMOS transistor. The pull-down network is connected to the node, a first reference voltage, the plurality of inputs and the clock signal. The N-type CMOS transistor is connected between the node and a second reference voltage. The N-type CMOS transistor is also connected to a complement of the clock signal. A method of the invention accepts a complement of a clock signal and pre-charges a node to a voltage less than a power supply voltage, in response to the complement of the clock signal. The method also accepts a plurality of input signals and accepts the clock signal. The method conditionally discharges the node, in response to the clock signal, on the basis of the plurality of input signals.

Abstract: A method or process of manufacturing on-chip capacitors on a VLSI device (or chip) is improved by utilizing a high-dielectric constant metal-insulator-metal (MIM) capacitor manufacturing process. The high-k constant MIM capacitor may include a lower electrode in a first metal layer of a VLSI device, a substantially thin layer of high-k insulator (e.g., silicon nitride at an interface of the first metal layer and a via, and an upper electrode form in a second metal layer. The via provides a channel between the second metal layer to the high-k insulator. The on-chip capacitors may be fabricated in a variety of configurations such as a parallel line, parallel plate or in a cross-over area of two different metal lines.

Abstract: A method or process of manufacturing on-chip bypass capacitors on a VLSI device (or chip) is improved by utilizing a high-dielectric constant metal-insulator-metal (MIM) capacitor manufacturing process. The high-k constant MIM capacitor may include a lower electrode in a first metal layer of a VLSI device, a substantially thin layer of high-k insulator (e.g., silicon nitride at an interface of the first metal layer and a via, and an upper electrode form in a second metal layer. The via provides a channel between the second metal layer to the high-k insulator.

Abstract: A ramp loading circuit for slowing current change in a circuit block. The circuit may include a plurality of load circuits placed in parallel with the circuit block and a control circuit. Each load circuit may provide a path for current flow when the load circuit is activated. Each load circuit may also be configured to allow a gradual decrease in current flow through the path when the load circuit is deactivated. The control circuit may be configured to deactivate each load circuit before the circuit block enters the sleep mode.