Patents by Inventor Osamu SHIRATA

Osamu SHIRATA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11862657
    Abstract: To achieve a size reduction of a semiconductor package while securing stability in mounting. Three terminals t1, t2, and t4 are individually arranged on a semiconductor package 10 having a rectangular shape as viewed in plan in such a manner that the center in the longitudinal direction of the semiconductor package 10 of each of the three terminals t1, t2, and t4 and the center in the longitudinal direction of each of the other terminals are not overlapped with each other as viewed from the side of the long side.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: January 2, 2024
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Osamu Shirata, Yusuke Hidaka
  • Publication number: 20220336516
    Abstract: To achieve a size reduction of a semiconductor package while securing stability in mounting. Three terminals t1, t2, and t4 are individually arranged on a semiconductor package 10 having a rectangular shape as viewed in plan in such a manner that the center in the longitudinal direction of the semiconductor package 10 of each of the three terminals t1, t2, and t4 and the center in the longitudinal direction of each of the other terminals are not overlapped with each other as viewed from the side of the long side.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Applicant: ASAHI KASEI MICRODEVICES CORPORATION
    Inventors: Osamu SHIRATA, Yusuke HIDAKA
  • Patent number: 11411038
    Abstract: To achieve a size reduction of a semiconductor package while securing stability in mounting. Three terminals t1, t2, and t4 are individually arranged on a semiconductor package 10 having a rectangular shape as viewed in plan in such a manner that the center in the longitudinal direction of the semiconductor package 10 of each of the three terminals t1, t2, and t4 and the center in the longitudinal direction of each of the other terminals are not overlapped with each other as viewed from the side of the long side.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: August 9, 2022
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Osamu Shirata, Yusuke Hidaka
  • Publication number: 20210020680
    Abstract: To achieve a size reduction of a semiconductor package while securing stability in mounting. Three terminals t1, t2, and t4 are individually arranged on a semiconductor package 10 having a rectangular shape as viewed in plan in such a manner that the center in the longitudinal direction of the semiconductor package 10 of each of the three terminals t1, t2, and t4 and the center in the longitudinal direction of each of the other terminals are not overlapped with each other as viewed from the side of the long side.
    Type: Application
    Filed: August 25, 2020
    Publication date: January 21, 2021
    Applicant: ASAHI KASEI MICRODEVICES CORPORATION
    Inventors: Osamu SHIRATA, Yusuke HIDAKA
  • Patent number: 10790328
    Abstract: To achieve a size reduction of a semiconductor package while securing stability in mounting. Three terminals t1, t2, and t4 are individually arranged on a semiconductor package 10 having a rectangular shape as viewed in plan in such a manner that the center in the longitudinal direction of the semiconductor package 10 of each of the three terminals t1, t2, and t4 and the center in the longitudinal direction of each of the other terminals are not overlapped with each other as viewed from the side of the long side.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 29, 2020
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Osamu Shirata, Yusuke Hidaka
  • Publication number: 20190165031
    Abstract: To achieve a size reduction of a semiconductor package while securing stability in mounting. Three terminals t1, t2, and t4 are individually arranged on a semiconductor package 10 having a rectangular shape as viewed in plan in such a manner that the center in the longitudinal direction of the semiconductor package 10 of each of the three terminals t1, t2, and t4 and the center in the longitudinal direction of each of the other terminals are not overlapped with each other as viewed from the side of the long side.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 30, 2019
    Applicant: ASAHI KASEI MICRODEVICES CORPORATION
    Inventors: Osamu SHIRATA, Yusuke HIDAKA
  • Patent number: D933618
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: October 19, 2021
    Assignee: ASAHI KASEI MICRODEVICES CORPORATION
    Inventors: Osamu Shirata, Yusuke Hidaka