Abstract: There is provided an ATM controller which can support setting or alteration of protocol processing, and more greatly reduce the load (overhead) of software processing. The ATM controller performs the processing of an ATM layer and an AAL layer between a terminal and an ATM network, and comprises cell transmit control moans for transferring a packet from a terminal side to an ATM network side while segmenting the packet into data cells, cell reception control means for reassembling data cells received from the ATM network side into a packet and transferring the packet to the terminal side, a rewritable memory for storing a firmware, and a microprocessor for performing a cell analysis and the processing corresponding to the analysis result.

Abstract: Disclosed herein is a computer system which comprises a plurality of input/output devices, an adapter device coupled to the plurality of input/output devices and a main processing unit for supplying an input/output request to each of the plurality of input/output devices through the adapter device. A plurality of input/output commands are respectively issued to the plurality of input/output devices from the main processing unit as one input/output start command. The adapter device specifies to which input/output devices the plurality of input/output commands included in the one input/output start command correspond. Further, the adapter device supplies input/output commands to the specified input/output devices respectively.

Abstract: An ATM switch for providing an electrical interconnection between a connection-oriented ATM LAN of an ATM system and a connectionless legacy LAN is provided.

Abstract: A network interface apparatus connected between a LAN adaptor possessed by a computer and a transceiver provided on a network includes a buffer memory for storing data, a first control circuit for communicating with the LAN adaptor, a second control circuit for communicating with the transceiver, and a processor for controlling the first and second control circuits to control the transfer of data between the LAN adaptor and the transceiver. The processor causes the buffer memory to store transmit data transmitted from the LAN adaptor and transmits the stored transmit data in the buffer memory to the transceiver in a transmission time zone which is allotted beforehand. The transmission time zone is determined by the processor on the basis of the reception of a synchronizing packet which is transferred on the network. Receive data received from the transceiver is selected by the processor so that only the selected receive data is sent to the LAN adaptor.

Abstract: A distributed memory computer system periodically performs memory copy among a plurality of computers by using general-purpose communication control devices and a transmission line of the CSMA/CD type. A master computer periodically generates a synchronizing packet, and transmits data for memory copy and normal data in a time slot immediately after the transmission of the synchronizing packet. Each computer other than the master computer transmits the data for memory copy and the normal data in its own time slot after the elapse of a predetermined time. The respective computers complete their transmissions within predetermined times. Since the time slots are assigned to the respective computers, the number of computers which may compete with each other on a transmission line can be restricted and each computer can be assured a periodic opportunity to transmit data.

Abstract: Communication control equipment for connecting a computer system to a network and supporting the computer system to set a plurality of connections on the network and perform parallel communication between computers.

Abstract: The voice mail system includes a voice mail exchanger and a mail server. A voice mail communication between a telephone and a terminal device, such as a client computer, is registered in a LAN based multi-media mail box. A PBX based voice mail apparatus and a LAN based multi-media mail system are integrated such that voice information can be commonly used and reused.

Abstract: An internetworking apparatus which handles a scale of a network flexibly without degrading high speed operation. A router manager and a plurality of routing accelerator modules for performing routing are connected to one another through a high speed bus, and a plurality of communication ports are connected to the respective routing accelerators independently of one another. The plurality of routing accelerators can perform the routing for reception data packet at high speed. If more routing accelerators are provided, the disposal to the networks having a small scale to a large scale can be readily realized.

Abstract: A frame strip method for a bridge circuit for transparently forwarding data between a plurality of LANs (Local Area Network) without frame infinite circulation. The numbers of transmission/receive frames are counted. In counting the number, the validity/invalidity of a transmission frame is judged in accordance with the kind of the transmission frame. The validity/invalidity and strip/receive of a receive frame are judged in accordance with the kind of the receive frame. In accordance with the numbers of valid transmission/receive frames, a receive frame is stripped from the transmission line if the condition of (transmission frame number)>(receive frame number) is met.

Abstract: Frontend LANs connecting plural stations are connected to plural nodes of a backbone LAN respectively. The backbone LAN is constituted by plural physical or logical links, and each node corresponds to each frontend LAN. A first data block is segmented into one or plural second data block units of fixed length and transferred to destination nodes, a bridge is provided in order to assemble the second data blocks into the first data block. The bridge can transmit the second data blocks to arbitrary links, and the receiving is performed through one link. The bridge a decoder also has a decoder for decoding whether the learning should be performed or not, based on the learning indication information existing in the second data block including the routing information.

Abstract: The present invention relates to an address filter method and unit to be used in a bridge unit or the like for connecting networks. The address filter unit carries out an address filter processing between a plurality of networks by using address information extracted from an incoming information frame registered in an entry table. In order to improve the processing efficiency of the address filter processing, the address filter unit includes timers corresponding to each address information registration, timer updating means for sequentially and intermittently advancing each timer value, and means for deleting registration of the address information corresponding to the timers from the entry table when a timer value becomes equal to or above a predetermined value.

Abstract: In a network having a plurality of node apparatus connected to a transmission line, each node apparatus segmenting a transmission message into information blocks of a predetermined length and transmitting them to the transmission line in the form of a fixed length packet (cell) having a source address, each node apparatus sequentially stores packets having different source addresses in vacant memory blocks of a buffer memory. There is written in each memory block the packet data as well as a next address pointer indicating a memory block in which the next received packet having the same source address is stored. When a packet containing the last information block of a message is received, stored in a read address queue is the address indicating the memory block which stores the first information block of the same packet.

Abstract: Messages are transferred among a plurality of nodes by segmenting each of the messages into a plurality of packets on a transmission loop, and a receiver circuit which reassembles the segmented packets into the original message by the use of message buffers is comprised in each of the nodes, to detect whether or not a packet having arrived is from a registered mate, so that when the mate of the packet is not registered, the packet having arrived is registered anew in an empty field in any of the message buffers, thereby to perform message buffering, and that when no empty field exists, the packet having arrived is returned as being unreceivable, whereupon the sending mate having received the packet resends it.

Abstract: Herein disclosed is a data communication system in which a plurality of node equipments are linked to a common signal transmission line so that the data may be communicated between the respective node equipments. The data communication system is characterized: in that at least one of the node equipments includes means for generating and transmitting repeatedly for a predetermined period the channel which contains a data transmission bit and a validity bit for the former bit; and in that each of the node equipments linked to the common signal transmission line partly sends out the data through said channel and partly makes the validity indicating bit indicate an invalid state, when the speed of said data is so slower than the predetermined period of said channel that the data to be sent out for the predetermined period are out of time thereby to make it possible to effect the data transmission at an arbitrary speed shorter than said predetermined period.

Abstract: A resistor is provided with a plurality of turn parts whose corners have an obtuse flexional angle in order to improve the relative resistance precision. A ladder resistor can be formed with a plurality of such resistors connected in series, and various electronic devices are formed employing the ladder resistor.