Abstract: A storage system according to the present invention includes a first storage device configured to receive a command from a command issuing apparatus, a second storage device configured to manage target data of the command, and a third storage device configured to form a copy pair with the second storage device for the target data and store the target data. When the target data is forwarded from the first storage device to the third storage device through the second storage device and stored in the third storage device, the second storage device stores the target data therein so that the target data is redundantly stored in the second storage device and the third storage device.

Abstract: A storage system according to the present invention includes a first storage device configured to receive a command from a command issuing apparatus, a second storage device configured to manage target data of the command, and a third storage device configured to form a copy pair with the second storage device for the target data and store the target data. When the target data is forwarded from the first storage device to the third storage device through the second storage device and stored in the third storage device, the second storage device stores the target data therein so that the target data is redundantly stored in the second storage device and the third storage device.

Abstract: The present invention makes it possible to process a plurality of commands included in a series of communication processes in a shared manner by a plurality of circuit parts, thereby improving reliability and processing performance. A semiconductor integrated circuit for communication (212) includes: a plurality of first circuit parts (2121) that are responsible for communicating with a higher-level apparatus (4); a plurality of second circuit parts (2122), which analyze a command included in a series of communication processes, and which share the processing of a plurality of commands included in the series of processes with another second circuit part; a common connector (2123) for connecting the first circuit parts to the second circuit parts; and a failure management part (2124), which, when a failure has occurred in any circuit part, causes the stoppage of processing by a stop-target circuit part that must stop processing.

Abstract: The present invention makes it possible to process a plurality of commands included in a series of communication processes in a shared manner by a plurality of circuit parts, thereby improving reliability and processing performance. A semiconductor integrated circuit for communication (212) includes: a plurality of first circuit parts (2121) that are responsible for communicating with a higher-level apparatus (4); a plurality of second circuit parts (2122), which analyze a command included in a series of communication processes, and which share the processing of a plurality of commands included in the series of processes with another second circuit part; a common connector (2123) for connecting the first circuit parts to the second circuit parts; and a failure management part (2124), which, when a failure has occurred in any circuit part, causes the stoppage of processing by a stop-target circuit part that must stop processing.

Abstract: An object of the present invention is to efficiently perform a data transfer by using a plurality of data transfer devices. A storage apparatus 10 includes: a channel control unit 11 having a first DMA 1142, a second DMA 1112, and a memory 113; a processor unit 12; and a drive control unit 13 that communicates with a storage device 17. When the channel control unit 11 transfers to a host computer 3 data stored in a cache memory 14, the first DMA 1142 receives from a processor unit 12 a setting of a first transfer parameter 151 for the first DMA 1142 containing a second transfer parameter 152 for the second DMA 1112, performs a first data transfer from the cache memory 14 to the memory 113 according to the first transfer parameter 151, and sets the second transfer parameter in the second DMA 1112 thereby to cause the second DMA 1112 to perform a data transfer from the memory 113 to the host computer 3.

Abstract: An efficient transfer of data including a plurality of data sections is achieved. In a data transfer system including a first DMA 1142 of a channel control unit 11 and an MP 122 of a processor unit 12 that sets a transfer parameter in the first DMA 1142, while CKD format data 1400 is transferred from a cache memory 14 to a memory 113 of the channel control unit 11, the MP 122 acquires a C field 1411 from the cache memory 14 and sets a transfer parameter in the first DMA 1142 on the basis of the acquired C field 1411, the transfer parameter having attached thereto the C field 1411 and being used for transferring a K field 1412 from the cache memory 14 to the memory 113. The first DMA 1142 retrieves the C field 1411 attached to the transfer parameter, stores the C field 1411 in the memory 113, and transfers the K field from the cache memory 14 to the memory 113 according to the transfer parameter.

Abstract: An object of the present invention is to efficiently perform a data transfer by using a plurality of data transfer devices. A storage apparatus 10 includes: a channel control unit 11 having a first DMA 1142, a second DMA 1112, and a memory 113; a processor unit 12; and a drive control unit 13 that communicates with a storage device 17. When the channel control unit 11 transfers to a host computer 3 data stored in a cache memory 14, the first DMA 1142 receives from a processor unit 12 a setting of a first transfer parameter 151 for the first DMA 1142 containing a second transfer parameter 152 for the second DMA 1112, performs a first data transfer from the cache memory 14 to the memory 113 according to the first transfer parameter 151, and sets the second transfer parameter in the second DMA 1112 thereby to cause the second DMA 1112 to perform a data transfer from the memory 113 to the host computer 3.

Abstract: An efficient transfer of data including a plurality of data sections is achieved. In a data transfer system including a first DMA 1142 of a channel control unit 11 and an MP 122 of a processor unit 12 that sets a transfer parameter in the first DMA 1142, while CKD format data 1400 is transferred from a cache memory 14 to a memory 113 of the channel control unit 11, the MP 122 acquires a C field 1411 from the cache memory 14 and sets a transfer parameter in the first DMA 1142 on the basis of the acquired C field 1411, the transfer parameter having attached thereto the C field 1411 and being used for transferring a K field 1412 from the cache memory 14 to the memory 113. The first DMA 1142 retrieves the C field 1411 attached to the transfer parameter, stores the C field 1411 in the memory 113, and transfers the K field from the cache memory 14 to the memory 113 according to the transfer parameter.

Abstract: The storage system includes a first memory device configured to store data sent from a host system, a first memory device controller configured to control read/write access of the data from/to the first memory device, an arithmetic circuit unit configured to calculate parity data based on the data, a second memory device configured to store the parity data, a second memory device controller configured to control read/write access of the parity data from/to the second memory device. With this storage system, read access speed of the first memory device is faster than read access speed of the second memory device.

Abstract: A channel control unit of a storage apparatus is provided with: a variable-length DMA (Direct Memory Access) that performs data transfer of variable-length data sent to or received from the host computer in accordance with an I/O request; a fixed-length DMA that performs data transfer of fixed-length data to and from the cache memory; and a buffer intervening between the variable-length DMA and the fixed-length DMA. In performing the data transfer of the fixed-length data to the cache memory, the fixed-length DMA divides the variable-length data into multiple sets of the fixed-length data each having a data size equivalent to a unit size of data managed in the cache memory, and adds a first integrity code to the last fixed-length data set of the fixed-length data sets generated by the division, the first integrity code being generated based on the entire variable-length data.

Abstract: A channel control unit of a storage apparatus is provided with: a variable-length DMA (Direct Memory Access) that performs data transfer of variable-length data sent to or received from the host computer in accordance with an I/O request; a fixed-length DMA that performs data transfer of fixed-length data to and from the cache memory; and a buffer intervening between the variable-length DMA and the fixed-length DMA. In performing the data transfer of the fixed-length data to the cache memory, the fixed-length DMA divides the variable-length data into multiple sets of the fixed-length data each having a data size equivalent to a unit size of data managed in the cache memory, and adds a first integrity code to the last fixed-length data set of the fixed-length data sets generated by the division, the first integrity code being generated based on the entire variable-length data.

Abstract: The storage system includes a first memory device configured to store data sent from a host system, a first memory device controller configured to control read/write access of the data from/to the first memory device, an arithmetic circuit unit configured to calculate parity data based on the data, a second memory device configured to store the parity data, a second memory device controller configured to control read/write access of the parity data from/to the second memory device. With this storage system, read access speed of the first memory device is faster than read access speed of the second memory device.

Abstract: A protocol chip and a bridge are connected to a first bus, while the bridge and a micro processor (MP) are connected to a second bus. The MP generates parameter information and writes it into a local memory (LM), and issues a write command which includes access destination information to this parameter information to a protocol chip. The bridge pre-fetches the parameter information from the LM using the access destination information within the write command which is transferred to the protocol chip via itself, and when receiving a read command from the protocol chip, transmits the parameter information which has been pre-fetched to the protocol chip via the first bus, without passing the read command through to the MP.

Abstract: A protocol chip and a bridge are connected to a first bus, while the bridge and a micro processor (MP) are connected to a second bus. The MP generates parameter information and writes it into a local memory (LM), and issues a write command which includes access destination information to this parameter information to a protocol chip. The bridge pre-fetches the parameter information from the LM using the access destination information within the write command which is transferred to the protocol chip via itself, and when receiving a read command from the protocol chip, transmits the parameter information which has been pre-fetched to the protocol chip via the first bus, without passing the read command through to the MP.