Abstract: The present invention discloses an apparatus of high dynamic-range CMOS image sensor and method thereof. The present invention utilize a pixel circuit outputting an output signal, wherein the pixel circuit has a photodiode and a plurality of transistors; and utilize a current source as a charge supplement unit to supply current into one end of the photodiode, and providing charges to the parasitic capacitor of the photodiode to delay saturation in the pixel circuit. In addition, a feedback circuit can be further designed connecting the pixel circuit. The feedback circuit receives the output signal from the pixel circuit and then outputs a control signal according to the output signal of the pixel circuit to control status of the charge supplement unit, and thereby increasing the dynamic range of the CMOS image sensor.

Abstract: The present invention discloses an apparatus of high dynamic-range CMOS image sensor and method thereof. The present invention utilize a pixel circuit outputting an output signal, wherein the pixel circuit has a photodiode and a plurality of transistors; and utilize a current source as a charge supplement unit to supply current into one end of the photodiode, and providing charges to the parasitic capacitor of the photodiode to delay saturation in the pixel circuit. In addition, a feedback circuit can be further designed connecting the pixel circuit. The feedback circuit receives the output signal from the pixel circuit and then outputs a control signal according to the output signal of the pixel circuit to control status of the charge supplement unit, and thereby increasing the dynamic range of the CMOS image sensor.

Abstract: A motion vector (MV) prediction method and a prediction apparatus thereof are applicable for a video image encoder/decoder to predict an MV of a video image. Firstly, segment a macroblock in the video image into microblocks. Then, configure a row memory and three register memories to register the MV required for prediction. Finally, the MV stored in the row memory or the register memories at a position corresponding to the current microblock to be predicted is used to predict the MV of the current microblock to be predicted in the current macroblock to be predicted. After the prediction is completed and moved to another macroblock or microblock, the MV stored in the row memory or the register memories is updated according to a predetermined storage updating condition.

Abstract: A method for automatically determining the region of interest from an image comprises the three steps of (a) analyzing content of the transformed coefficients of an image after a discrete signal transformation and partitioning an image into the interested region and background region that are based on p×p-pixel sub-blocks for performing classification; (b) locating the central point of the interested sub-blocks; and (c) integrating a plurality of the interested sub-blocks from said central point to the boundary of an image to generate a closed and continued region of interest by using a image processing technique with considering the bit-rate requirement.

Abstract: A reconfigurable apparatus with a high usage rate in hardware is disclosed, which comprises at least one reconfigurable unit that has a plurality of processing units and at least one switch box connected to the processing units. The reconfigurable unit receives at least one reconfiguration signal to dynamically configure the processing units and the switch boxes as a new functional unit.

Abstract: A method for automatically determining the region of interest from an image comprises the three steps of (a) analyzing content of the transformed coefficients of an image after a discrete signal transformation and partitioning an image into the interested region and background region that are based on p×p-pixel sub-blocks for performing classification; (b) locating the central point of the interested sub-blocks; and (c) integrating a plurality of the interested sub-blocks from said central point to the boundary of an image to generate a closed and continued region of interest by using a image processing technique with considering the bit-rate requirement.

Abstract: A method and apparatus of constructing a hardware architecture for transform functions is disclosed, which uses a single-input-parallel-output method for processing operations. The transform function has operations of multiplication, path-selection, and accumulation to be executed. The fixed-one-input multipliers first multiply an input signal by all transform coefficients. Then a path-selection unit determines correct signal paths and delivers product results to the corresponding accumulators for processing accumulation. Finally, multipliers perform the multiplications of the accumulated values and a constant to obtain output signals.

Abstract: An energy saving multiplication device and its method is disclosed. The multiplication device includes a dynamic range determination unit, a Booth encoding/decoding unit and a counter array. The dynamic range determination unit determines dynamic ranges of the numerical values to be multiplied together and outputs after processing according to the dynamic-range size relation of the input data. The Booth encoding/decoding unit couples to the dynamic range determination unit. The counter array couples to the Booth encoding/decoding unit for accumulating the partial products to obtain the products of the input data.

Abstract: An arithmetic device with low power consumption includes master latches, a dynamic range detection unit, slave latches, an operation unit, and a word-length restoration unit. In the arithmetic device, the master latches latch a plurality of (such as two) input data. The dynamic range detection unit detects the effective dynamic range of these input data. The slave latches latch the values of the effective dynamic-range bits of these input data. The operation unit performs predetermined operations of the bits of these effective dynamic range to obtaing an operation result. Since the operation unit only performs operations of the bits of the effective dynamic range, the circuit corresponding to other bits will not demonstrate switching of power consumption, thereby lowering the overall power consumption. Furthermore, the word-length restoration unit will complement the operation result to its original output length in association with the sign of the operation result, for obtaining the correct operation result.

Abstract: An energy saving multiplication device and its method is disclosed. The multiplication device comprises a dynamic range determination unit, a Booth encoding/decoding unit and a counter array. The dynamic range determination unit determines dynamic ranges of the numerical values to be multiplied together and outputs after processing according to the dynamic-range size relation of the input data. The Booth encoding/decoding unit couples to the dynamic range determination unit. The counter array couples to the Booth encoding/decoding unit for accumulating the partial products to obtain the products of the input data.

Abstract: A programmable finite impulse response processor, by which a convolution calculation between input data and filter coefficients is performed based on Booth algorithm. The processor include a pre-processing unit, data latches, a configurable connection unit, Booth decoders, coefficient registers, a path control unit, and a post-processing unit. The pre-processing unit is used to partition the input data into a pipeline sequence which include a plurality of sequence units in a Booth format. According to both the dynamic ranges of the input data and of the filter coefficients, the configurable connection unit is used to select certain parts of the sequence units for the convolution calculation, so that a dynamic data range is scaleable by the processor. By Booth decoders, the selected sequence units are decoded and multiplied by corresponding filter coefficients stored in the coefficient registers.