Patents by Inventor Oscar Fernando Castañeda Fernandez

Oscar Fernando Castañeda Fernandez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11409527
    Abstract: A parallel processor in associative content-addressable memory (PPAC) is provided. Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. Most existing PIM architectures are either general-purpose but only support atomistic operations, or are specialized to accelerate a single task. The PPAC described herein provides a novel in-memory accelerator that supports a range of matrix-vector-product (MVP)-like operations that find use in traditional and emerging applications. PPAC is, for example, able to accelerate low-precision neural networks, exact/approximate hash lookups, cryptography, and forward error correction. The fully-digital nature of PPAC enables its implementation with standard-cell-based complementary metal-oxide-semiconductor (CMOS), which facilitates automated design and portability among technology nodes.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: August 9, 2022
    Assignee: Cornell University
    Inventors: Christoph Emanuel Studer, Oscar Fernando Castañeda Fernandez
  • Publication number: 20210281302
    Abstract: Finite-alphabet beamforming for multi-antenna wideband systems is provided. The combination of massive multi-user multiple-input multiple-output (MU-MIMO) technology and millimeter-wave (mmWave) communication enables unprecedentedly high data rates for radio frequency (RF) communications. In such systems, beamforming must be performed at extremely high rates over hundreds of antennas. For example, spatial equalization applies beamforming in the uplink to mitigate interference among user equipment (UEs) at a base station (BS). Finite-alphabet equalization provides a new paradigm that restricts the entries of a spatial equalization matrix to low-resolution numbers, enabling high-throughput, low-power, and low-cost equalization hardware. Similarly, precoding applies beamforming in the downlink to maximize the reception of a signal transmitted from a BS to a target UE. Finite-alphabet precoding can be applied in the downlink to similarly improve power and cost in precoding hardware.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 9, 2021
    Inventors: Oscar Fernando Castañeda Fernandez, Christoph Emanuel Studer
  • Patent number: 11115095
    Abstract: Finite-alphabet beamforming for multi-antenna wideband systems is provided. The combination of massive multi-user multiple-input multiple-output (MU-MIMO) technology and millimeter-wave (mmWave) communication enables unprecedentedly high data rates for radio frequency (RF) communications. In such systems, beamforming must be performed at extremely high rates over hundreds of antennas. For example, spatial equalization applies beamforming in the uplink to mitigate interference among user equipment (UEs) at a base station (BS). Finite-alphabet equalization provides a new paradigm that restricts the entries of a spatial equalization matrix to low-resolution numbers, enabling high-throughput, low-power, and low-cost equalization hardware. Similarly, precoding applies beamforming in the downlink to maximize the reception of a signal transmitted from a BS to a target UE. Finite-alphabet precoding can be applied in the downlink to similarly improve power and cost in precoding hardware.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 7, 2021
    Assignee: Cornell University
    Inventors: Oscar Fernando Castañeda Fernandez, Christoph Emanuel Studer
  • Publication number: 20210019147
    Abstract: A parallel processor in associative content-addressable memory (PPAC) is provided. Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. Most existing PIM architectures are either general-purpose but only support atomistic operations, or are specialized to accelerate a single task. The PPAC described herein provides a novel in-memory accelerator that supports a range of matrix-vector-product (MVP)-like operations that find use in traditional and emerging applications. PPAC is, for example, able to accelerate low-precision neural networks, exact/approximate hash lookups, cryptography, and forward error correction. The fully-digital nature of PPAC enables its implementation with standard-cell-based complementary metal-oxide-semiconductor (CMOS), which facilitates automated design and portability among technology nodes.
    Type: Application
    Filed: July 15, 2020
    Publication date: January 21, 2021
    Inventors: Christoph Emanuel Studer, Oscar Fernando Castañeda Fernandez