Patents by Inventor Oscar Ojeda
Oscar Ojeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948848Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.Type: GrantFiled: February 12, 2019Date of Patent: April 2, 2024Assignee: Intel CorporationInventors: Jeremy Ecton, Oscar Ojeda, Leonel Arana, Suddhasattwa Nad, Robert May, Hiroki Tanaka, Brandon C. Marin
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Publication number: 20240101413Abstract: Disclosed herein are microelectronics package architectures having self-aligned air gaps and methods of manufacturing the same. The microelectronics packages may include first and second substrates, first and second traces, and a photosensitive material. The first trace may be attached to the first substrate and comprise a first sidewall. The second trace may be attached to the first substrate and comprise a second sidewall. The second traced may be spaced a distance from the first trace with the second sidewall facing the first sidewall. First and second portions of the photosensitive material may be attached to the first and second sidewalls, respectively. The second substrate may be attached to the first and second traces. The first and second substrates and the first and second traces may form the air gap in between the first and second traces.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Inventors: Jeremy D. Ecton, Brandon C. Marin, Srinivas Venkata Ramanuja Pietambaram, Oladeji Fadayomi, Oscar Ojeda
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Publication number: 20230415452Abstract: Provided herein are monostable adhesive interfaces, for example, a sacrificial bond interface, and self-repairing composite materials that are a layered assembly of magnetic materials and deformable adhesive materials such as a non-linear adhesive material and/or a mechanical adhesive. Also provided is a method for constructing a sacrificial bond composite material and the sacrificial bond composite material constructed by the method.Type: ApplicationFiled: June 22, 2023Publication date: December 28, 2023Applicant: The Texas A&M University SystemInventors: Vanessa Restrepo, Oscar Ojeda
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Patent number: 11817349Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.Type: GrantFiled: March 5, 2020Date of Patent: November 14, 2023Assignee: Intel CorporationInventors: Jeremy Ecton, Brandon C. Marin, Leonel Arana, Matthew Tingey, Oscar Ojeda, Hsin-Wei Wang, Suddhasattwa Nad, Srinivas Pietambaram, Gang Duan
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Patent number: 11721631Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.Type: GrantFiled: May 24, 2022Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Jeremy D. Ecton, Hiroki Tanaka, Oscar Ojeda, Arnab Roy, Vahidreza Parichehreh, Leonel R. Arana, Chung Kwang Tan, Robert A. May
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Patent number: 11652036Abstract: Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.Type: GrantFiled: April 2, 2018Date of Patent: May 16, 2023Inventors: Jeremy Ecton, Hiroki Tanaka, Kristof Kuwawi Darmawikarta, Oscar Ojeda, Arnab Roy, Nicholas Haehn
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Publication number: 20230087810Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Jeremy D. ECTON, Kristof DARMAWIKARTA, Suddhasattwa NAD, Oscar OJEDA, Bai NIE, Brandon C. MARIN, Gang DUAN, Jacob VEHONSKY, Onur OZKAN, Nicholas S. HAEHN
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Patent number: 11528811Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.Type: GrantFiled: June 1, 2021Date of Patent: December 13, 2022Assignee: Intel CorporationInventors: Jeremy Ecton, Nicholas Haehn, Oscar Ojeda, Arnab Roy, Timothy White, Suddhasattwa Nad, Hsin-Wei Wang
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Publication number: 20220285278Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.Type: ApplicationFiled: May 24, 2022Publication date: September 8, 2022Inventors: Jeremy D. ECTON, Hiroki TANAKA, Oscar OJEDA, Arnab ROY, Vahidreza PARICHEHREH, Leonel R. ARANA, Chung Kwang TAN, Robert A. MAY
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Patent number: 11373951Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.Type: GrantFiled: March 27, 2018Date of Patent: June 28, 2022Assignee: Intel CorporationInventors: Jeremy D. Ecton, Hiroki Tanaka, Oscar Ojeda, Arnab Roy, Vahidreza Parichehreh, Leonel R. Arana, Chung Kwang Tan, Robert A. May
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MULTI-STEP ISOTROPIC ETCH PATTERNING OF THICK COPPER LAYERS FOR FORMING HIGH ASPECT-RATIO CONDUCTORS
Publication number: 20220199427Abstract: An integrated circuit device, comprising a substrate comprising a dielectric material and a conductor on or within the dielectric material of the substrate. The conductor comprises a first portion comprising a first sloped sidewall, wherein a first base width of the first portion is greater than a first top width of the first portion. The conductor also comprises a second portion over the first portion, the second portion comprising a second sloped sidewall, wherein a second base width of the upper portion is greater than both a second top width of the second portion and the first top width of the first portion.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Oladeji Fadayomi, Jeremy Ecton, Oscar Ojeda -
Publication number: 20210289638Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.Type: ApplicationFiled: June 1, 2021Publication date: September 16, 2021Applicant: INTEL CORPORATIONInventors: Jeremy Ecton, Nicholas Haehn, Oscar Ojeda, Arnab Roy, Timothy White, Suddhasattwa Nad, Hsin-Wei Wang
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Publication number: 20210280463Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.Type: ApplicationFiled: March 5, 2020Publication date: September 9, 2021Applicant: INTEL CORPORATIONInventors: Jeremy Ecton, Brandon C. Marin, Leonel Arana, Matthew Tingey, Oscar Ojeda, Hsin-Wei Wang, Suddhasattwa Nad, Srinivas Pietambaram, Gang Duan
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Patent number: 11116084Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.Type: GrantFiled: September 27, 2017Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Jeremy Ecton, Nicholas Haehn, Oscar Ojeda, Arnab Roy, Timothy White, Suddhasattwa Nad, Hsin-Wei Wang
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Patent number: 10798817Abstract: Apparatus and methods are provided for flexible and stretchable circuits. In an example, a method can include forming a first flexible conductor on a substrate, the first flexible conductor including a first conductive trace surrounded on three sides by a first dielectric, and forming a second flexible conductor on top of the first flexible conductor, the first flexible conductor located between the second flexible conductor and the substrate, the second flexible conductor including a second conductive trace surrounded by a second dielectric.Type: GrantFiled: December 11, 2015Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Aleksandar Aleksov, Javier Soto Gonzalez, Meizi Jiao, Shruti R. Jaywant, Oscar Ojeda, Sashi S. Kandanur, Srinivas Venkata Ramanuja Pietambaram, Roy Dittler, Rajat Goyal, Dilan Seneviratne
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Publication number: 20200258800Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.Type: ApplicationFiled: February 12, 2019Publication date: August 13, 2020Inventors: Jeremy ECTON, Oscar OJEDA, Leonel ARANA, Suddhasattwa NAD, Robert MAY, Hiroki TANAKA, Brandon C. MARIN
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Publication number: 20200236795Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.Type: ApplicationFiled: September 27, 2017Publication date: July 23, 2020Applicant: INTEL CORPORATIONInventors: Jeremy Ecton, Nicholas Haehn, Oscar Ojeda, Arnab Roy, Timothy White, Suddhasattwa Nad, Hsin-Wei Wang
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Patent number: 10515824Abstract: A method of anisotropic etching comprises forming a metal layer above a substrate. A mask layer is formed on the metal layer with openings defined in the mask layer to expose portions of the metal layer. The exposed portions of the metal layer are introduced to an active etchant solution that includes nanoparticles as an insoluble banking agent. In further embodiments, the exposed portions of the metal layer are introduced to a magnetic and/or an electrical field.Type: GrantFiled: January 11, 2018Date of Patent: December 24, 2019Assignee: Intel CorporationInventors: Jeremy Ecton, Leonel Arana, Nicholas S. Haehn, Hsin-Wei Wang, Oscar Ojeda, Arnab Roy
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Publication number: 20190304890Abstract: Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.Type: ApplicationFiled: April 2, 2018Publication date: October 3, 2019Applicant: Intel CorporationInventors: Jeremy Ecton, Hiroki Tanaka, Kristof Kuwawi Darmawikarta, Oscar Ojeda, Arnab Roy, Nicholas Haehn
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Publication number: 20190304912Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.Type: ApplicationFiled: March 27, 2018Publication date: October 3, 2019Applicant: INTEL CORPORATIONInventors: Jeremy D. Ecton, Hiroki Tanaka, Oscar Ojeda, Arnab Roy, Vahidreza Parichehreh, Leonel R. Arana, Chung Kwang Tan, Robert A. May