Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

Abstract: An integrated circuit including a memory array and a physical unclonable function array is obtained by causing metal back sputtering in specific regions of the integrated circuit during ion beam etch. MRAM pillars within the memory array have larger widths than the underlying bottom electrodes while those within the physical unclonable function array have smaller widths than the underlying bottom electrodes. Metal residue deposited over tunnel barrier layers causes random electrical shorting of some of the MRAM pillars within the physical unclonable function array.

Abstract: An interconnect structure and techniques for fabrication thereof having a partial sidewall liner are provided. In one aspect, the interconnect structure includes: a substrate; a dielectric disposed on the substrate having at least one feature present therein; a barrier layer lining the at least one feature; a seed enhancement liner disposed over the barrier layer along sidewalls of the at least one feature, wherein the seed enhancement liner is present along only a middle portion of the sidewalls of the at least one feature; and at least one interconnect disposed within the at least one feature over the barrier layer and the seed enhancement liner.

Abstract: Provided are embodiments for method of fabricating a dual damascene crossbar array. The method includes forming a bottom electrode layer on a substrate and forming a first memory device on the bottom electrode layer. The method also includes forming a dual damascene structure on the first memory device, wherein the dual damascene structure includes a top electrode layer and a first via, wherein the first via is formed between the first memory device and the top electrode layer. Also provided are embodiments for the dual damascene crossbar and embodiments for disabling memory devices of the dual damascene crossbar array.

Abstract: An interconnect structure of an integrated circuit (IC) in which dielectric material defines upper and lower cavities and a via cavity communicative with the upper and lower cavities at upper and lower ends thereof. The interconnect structure includes first conductive material filling the upper and lower cavities to form upper and lower lines, respectively and second conductive material filling the via cavity from the upper end thereof to the lower end thereof to form a via electrically communicative with the upper and lower lines.

Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

Abstract: An interconnect structure, and a method for forming the same includes forming recess within a dielectric layer and conformally depositing a barrier layer within the recess. A cobalt-infused ruthenium liner is formed above the barrier layer, the cobalt containing ruthenium liner formed by stacking a second liner above a first liner, the first liner positioned above the barrier layer. The first liner includes ruthenium while the second liner includes cobalt. Cobalt atoms migrate from the second liner to the first liner forming the cobalt-infused ruthenium liner. A conductive material is deposited above the cobalt-infused ruthenium liner to fill the recess followed by a capping layer made of cobalt.

Abstract: An interconnect structure of an integrated circuit (IC) in which dielectric material defines upper and lower cavities and a via cavity communicative with the upper and lower cavities at upper and lower ends thereof. The interconnect structure includes first conductive material filling the upper and lower cavities to form upper and lower lines, respectively and second conductive material filling the via cavity from the upper end thereof to the lower end thereof to form a via electrically communicative with the upper and lower lines.

Abstract: A low temperature deposited (400° C. or less) dielectric passivation layer is formed on physically exposed surfaces of a material stack including a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode. A laser anneal is then performed to improve the physical and chemical properties of the low temperature deposited dielectric passivation layer, without negatively impacting the multilayered MTJ pillar.

Abstract: An integrated circuit including a memory array and a physical unclonable function array is obtained by causing metal back sputtering in specific regions of the integrated circuit during ion beam etch. MRAM pillars within the memory array have larger widths than the underlying bottom electrodes while those within the physical unclonable function array have smaller widths than the underlying bottom electrodes. Metal residue deposited over tunnel barrier layers causes random electrical shorting of some of the MRAM pillars within the physical unclonable function array.

Abstract: An interconnect structure, and a method for forming the same includes forming recess within a dielectric layer and conformally depositing a barrier layer within the recess. A cobalt-infused ruthenium liner is formed above the barrier layer, the cobalt containing ruthenium liner formed by stacking a second liner above a first liner, the first liner positioned above the barrier layer. The first liner includes ruthenium while the second liner includes cobalt. Cobalt atoms migrate from the second liner to the first liner forming the cobalt-infused ruthenium liner. A conductive material is deposited above the cobalt-infused ruthenium liner to fill the recess followed by a capping layer made of cobalt.

Abstract: Method and apparatus for a capacitive structure. The capacitive structure includes a material stack having a deep trench formed therein. The material stack includes alternating vertical and semi-ovoid sidewall surfaces. The material stack further includes alternating metallization layers and dielectric layers. At least one of the semi-spheroidal sidewall surfaces is formed in a sidewall of at least one of the dielectric layers in the deep trench. At least one of the vertical sidewall surfaces is a sidewall surface of at least one metallization layer in the deep trench.

Abstract: A buried metal-insulator-metal (MIM) capacitor with landing pads is formed between first and second semiconductor substrates. The landing pads provide increased area for contacting which may decrease the contact resistors of the capacitor. The area of the buried MIM capacitor can be varied to provide a tailored capacitance. The buried MIM capacitor is thermally stable since the MIM capacitor includes refractory metal or metal alloy layers as the capacitor plates.

Abstract: A low temperature deposited (400° C. or less) dielectric passivation layer is formed on physically exposed surfaces of a material stack including a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode. A laser anneal is then performed to improve the physical and chemical properties of the low temperature deposited dielectric passivation layer, without negatively impacting the multilayered MTJ pillar.

Abstract: Devices and methods that can facilitate hybrid sidewall barrier and low resistance interconnect components are provided. According to an embodiment, a device can comprise a first interconnect material layer that can have a first opening that can comprise a first discontinuous barrier liner coupled to first sidewalls of the first opening and a first continuous barrier layer coupled to the first discontinuous barrier liner and the first sidewalls. The device can further comprise a second interconnect material layer coupled to the first interconnect material layer, the second interconnect material layer can have a second opening that can comprise a second discontinuous barrier liner coupled to second sidewalls of the second opening, a second continuous barrier layer coupled to the second discontinuous barrier liner and the second sidewalls.

Abstract: Magnetic structures including magnetic inductors and magnetic tunnel junction (MTJ)-containing structures that have tapered sidewalls are formed without using an ion beam etch (IBE). The magnetic structures are formed by providing a material stack of a dielectric capping layer and a sacrificial dielectric material layer above a lower interconnect level. First and second etching steps are performed to pattern the sacrificial dielectric material layer and the dielectric capping layer such that a patterned dielectric capping layer is provided with a tapered sidewall. After removing the sacrificial dielectric material layer, a magnetic material-containing stack is formed within the opening in the patterned dielectric capping layer and atop the patterned dielectric capping layer. A planarization process is then employed to pattern the magnetic-containing stack by removing the magnetic material-containing stack that is located atop the patterned dielectric capping layer.

Abstract: A magnetic tunnel junction (MTJ) structure having faceted sidewalls is formed on a conductive landing pad that is present on a surface of an electrically conductive structure embedded in a dielectric material layer. No metal ions are re-sputtered onto the sidewalls of the MTJ structure during the patterning of the MTJ material stack that provides the MTJ structure. The absence of re-sputtered metal on the MTJ structure sidewalls reduces the risk of shorts.

Abstract: According to embodiments of the present invention, a semiconductor wafer includes a substrate and an interlayer dielectric located on the substrate. The interlayer dielectric includes an interconnect. A barrier layer is located in between the interconnect and the interlayer dielectric. A semi-liner layer is located in between the interconnect and the barrier layer. The interlayer dielectric, the interconnect, and barrier layer form a substantially planar surface opposite the substrate. The interconnect has an interconnect height from a base to the substantially planar surface and a semi-liner height of the semi-liner layer is less than the interconnect height such that liner layer does not extend to the planar surface.

Abstract: A semiconductor structure includes a substrate. A first metallization layer is disposed on the substrate. A second metallization layer is disposed on the first metallization layer and having one or more openings, wherein at least one of the one or more openings is configured to expose a top surface of the first metallization layer. A polymer-adhering liner layer is disposed on sidewalls of the at least one of the one more openings in the second metallization layer. A dielectric polymer is disposed in the at least one of the one or more openings in the second metallization layer and on the polymer-adhering liner layer. The dielectric polymer is configured to seal an air gap in the dielectric polymer.

Abstract: An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.