Abstract: Some examples of the disclosure are directed to systems, apparatus, and methods for temperature detection using multiple temperature controllers each having distributed temperature sensors that allow reading multiple sensor outputs in parallel for a wide range of covered area. The temperature controller may also have logic to calculate a local temperature controller maximum temperature, a maximum temperature of all sensors, provide software access to each sensor, easy software enablement through a software interface that allows access earlier than when chip operating system (OS) is booted, and the ability to enable and mask individual sensors or sensor groups through software.

Abstract: Some examples of the disclosure are directed to systems, apparatus, and methods for temperature detection using multiple temperature controllers each having distributed temperature sensors that allow reading multiple sensor outputs in parallel for a wide range of covered area. The temperature controller may also have logic to calculate a local temperature controller maximum temperature, a maximum temperature of all sensors, provide software access to each sensor, easy software enablement through a software interface that allows access earlier than when chip operating system (OS) is booted, and the ability to enable and mask individual sensors or sensor groups through software.

Abstract: One embodiment of the present invention includes a system for managing power to a plurality of devices-under-test (DUTs). The system comprises a DUT test system configured to perform at least one test associated with operation of the DUTs and to monitor current associated the at least one test of the plurality of DUTs. The DUT test system can communicate an instruction to a subset of the plurality of DUTs to cancel the at least one test if the monitored current is greater than a predetermined threshold. Each of the plurality of DUTs can comprise restart logic configured to restart the at least one test of the subset of the plurality of DUTs after being cancelled in response to the instruction.

Abstract: One embodiment of the present invention includes a system for managing power to a plurality of devices-under-test (DUTs). The system comprises a DUT test system configured to perform at least one test associated with operation of the DUTs and to monitor current associated the at least one test of the plurality of DUTs. The DUT test system can communicate an instruction to a subset of the plurality of DUTs to cancel the at least one test if the monitored current is greater than a predetermined threshold. Each of the plurality of DUTs can comprise restart logic configured to restart the at least one test of the subset of the plurality of DUTs after being cancelled in response to the instruction.

Abstract: A system comprises a multi-core silicon-on-chip (SOC) device. The SOC device includes a core module, a test data shift path, a core power control module, and an emulation control module. The core module includes a TAP controller and a plurality of data registers. The test data shift path is operable to transport data shifted out of one or more of the data registers. The core power control module is operable to control the power status of the core module. The emulation control module includes a plurality of alternative registers operable to shift data into the test data shift path in the event that the core module is powered down by the core power control module such that the shift path continues uninterrupted. The emulation control module remains powered on regardless of the power status of the core module.

Abstract: A system comprises a multi-core silicon-on-chip (SOC) device. The SOC device includes a core module, a test data shift path, a core power control module, and an emulation control module. The core module includes a TAP controller and a plurality of data registers. The test data shift path is operable to transport data shifted out of one or more of the data registers. The core power control module is operable to control the power status of the core module. The emulation control module includes a plurality of alternative registers operable to shift data into the test data shift path in the event that the core module is powered down by the core power control module such that the shift path continues uninterrupted. The emulation control module remains powered on regardless of the power status of the core module.