Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

Abstract: In some embodiments, integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate are presented.

Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

Abstract: An imaging system may include an integrated circuit package that includes an image sensor die mounted in a flip chip configuration to a package substrate. The image sensor die may be a backside illumination sensor die. The image sensor die may include an imaging device structure formed over a carrier layer. Through-silicon vias formed in the carrier layer may couple imaging device circuitry in the imaging device structure to conductive bumps on the carrier layer that are coupled to metal interconnects. A ball grid array may be formed on a surface of the package substrate that may be coupled to the conductive bumps. A glass lid may be attached to the image sensor die using attachment structures such that an air gap is formed between the glass lid and the image sensor die. Package sealing material may be deposited between the image sensor die and the package substrate.

Abstract: An imaging system may include an integrated circuit package that includes an image sensor die mounted in a flip chip configuration to a package substrate. The image sensor die may be a backside illumination sensor die. The image sensor die may include an imaging device structure formed over a carrier layer. Through-silicon vias formed in the carrier layer may couple imaging device circuitry in the imaging device structure to conductive bumps on the carrier layer that are coupled to metal interconnects. A ball grid array may be formed on a surface of the package substrate that may be coupled to the conductive bumps. A glass lid may be attached to the image sensor die using attachment structures such that an air gap is formed between the glass lid and the image sensor die. Package sealing material may be deposited between the image sensor die and the package substrate.

Abstract: In some embodiments, integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate are presented.

Abstract: In one embodiment, the present invention includes a method for depositing lead-free bumps on a package substrate, depositing an alloy material on the lead-free bumps, attaching a semiconductor die including conductive bumps to the package substrate so that the conductive bumps contact the alloy material, and heating attached components to reflow the alloy material to form a joint therebetween. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for depositing lead-free bumps on a package substrate, depositing an alloy material on the lead-free bumps, attaching a semiconductor die including conductive bumps to the package substrate so that the conductive bumps contact the alloy material, and heating attached components to reflow the alloy material to form a joint therebetween. Other embodiments are described and claimed.

Abstract: In some embodiments, an integrated circuit package includes a substrate and a heat spreader coupled to the substrate by fasteners. Thermal interface material thermally couples the die to the heat spreader. The heat spreader is provided over the die and is attached to the substrate with fasteners rather than a sealant-adhesive. Some examples of suitable fasteners may include rivets, barbed connectors, and gripping clips.