Abstract: A binary input signal, V.sub.IN, having a minimum high level value, V.sub.INHMIN, is directly applied to the gate electrode of a pull-up transistor whose conduction path is connected between a first power terminal and an output terminal. V.sub.IN is also applied via level shift circuitry to the gate electrode of a pull-down transistor whose conduction path is connected between the output terminal and a second power terminal. V.sub.IN is level shifted in the positive direction by a preselected voltage level whereby the pull-down transistor is turned-on even when its threshold voltage is approximately equal to V.sub.INHMIN.

Abstract: First and second networks each comprised of two low-on-impedance transistors having their conduction paths connected in series are connected between first and second circuit outputs and a power terminal. In response to a signal transition of one polarity the two transistors of one network are momentarily turned-on to clamp its associated output to the power terminal. In response to a signal transition of opposite polarity the two transistors of the other network are momentarily turned-on to clamp its associated output to the power terminal.

Abstract: A circuit responsive to pulses on first and second input signal lines for blocking the propagation of these pulses and inhibiting the production of corresponding pulses on output lines when pulses are present at the same time on the input lines and for producing output pulses corresponding to the pulses on the input lines when there is no coincidence or concurrence of pulses on the two input lines.

Abstract: First and second low-ON-impedance switching transistors driven by complementary signals are connected between first and second outputs, respectively, and a first power terminal to which is applied a first voltage level. First and second high-ON-impedance load devices are connected between the first and second outputs, respectively, and a second power terminal to which is applied a second voltage level. The conduction paths of a first and a second normally non-conducting low-ON-impedance transistors are connected in parallel with the first and second load devices, respectively.

Abstract: A logic level converter for translating an input signal that swings between first and second voltage levels to an output signal that swings between third and fourth voltage levels. The input signal and its complement are first translated to the desired output levels in a pair of conventional CMOS inverters to produce complementary logic signals. The faster edge of each translated logic signal is used by logic means to control the output signal. Specifically, the leading edge of one logic signal and the trailing edge of the other logic signal are used to control the output signal. The resulting logic level shift circuit provides both fast rise and fall times, and substantially equal propagation delays for both high-to-low and low-to-high signal transitions.