Abstract: A memory device includes a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to an operation cycle of another access unit whose form factor is different from that of the access unit.

Abstract: A memory device includes a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to an operation cycle of another access unit whose form factor is different from that of the access unit.

Abstract: A memory device includes a plurality of memories, a plurality of access units, and a controller configured to control data from an access unit according to an operation cycle of another access unit whose form factor is different from that of the access unit. A resistor can be shared by the plurality of memories for impedance matching, which can shorten calibration time.

Abstract: A memory device comprising: a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to operation cycle different to another access unit whose form factor is different to that of the access unit.

Abstract: A system may include: a first memory device; a second memory device; a third memory device; and a fourth memory device, wherein the first memory device to the fourth memory device are configured to share a resistor for impedance matching, wherein the first memory device to the fourth memory device are coupled to have a chain shape, wherein the forth memory device generates a completion signal when performance is completed and the first memory device receives the completion signal provided from the fourth memory device.

Abstract: A memory device comprising: a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to operation cycle different to another access unit whose form factor is different to that of the access unit.

Abstract: A memory device comprising: a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to operation cycle different to another access unit whose form factor is different to that of the access unit.

Abstract: A memory device comprising: a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to operation cycle different to another access unit whose form factor is different to that of the access unit.

Abstract: A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

Abstract: A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

Abstract: A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

Abstract: A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

Abstract: A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

Abstract: A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

Abstract: A data processing device includes a controller. The controller includes a compression circuit configured to compare a plurality of data groups, each of which has a first burst length and is transmitted in units of an input/output width, with a predetermined pattern, and perform data compression on the data groups based on a result of comparison. The controller further includes a compression data restructuring circuit configured to generate a transmission data group by restructuring the compressed data group to have a second burst length.

Abstract: A data processing device includes a compression circuit and a padding circuit. The compression circuit is configured to compare pairs of two contiguous bits within data composed of 2n bits (where n is a natural number), and compress the data based on a result of the comparison. The padding circuit is configured to generate transmission data of 2n bits by padding the compressed data with a dummy pad.

Abstract: A data processing apparatus includes a controller configured to provide, using a unified connector, group data processing information for a processing operation of a data group processed based on the same data processing information. The data group comprises a plurality data transmitted or received through a plurality of connectors. An operation unit is configured to decode and/or encode the data group based on the group data processing information.

Abstract: A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

Abstract: The semiconductor device includes: a first die configured to include a first input pad and a first output pad; and a second die configured to include a second input pad and a second output pad. The second die corrects a level of an output voltage in response to a feedback reference voltage applied from the first output pad to the second input pad.

Abstract: The semiconductor device includes: a first die configured to include a first input pad and a first output pad; and a second die configured to include a second input pad and a second output pad. The second die corrects a level of an output voltage in response to a feedback reference voltage applied from the first output pad to the second input pad.